Merge branch 'master' of github.com:steveicarus/iverilog

This commit is contained in:
Stephen Williams 2012-04-10 15:31:32 -07:00
commit e55af496e5
6 changed files with 18 additions and 9 deletions

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@ -200,7 +200,7 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
// Special case: The l-value is an entire memory, or array
// slice. This is, in fact, an error in l-values. Detect the
// situation by noting if the index count is less then the
// situation by noting if the index count is less than the
// array dimensions (unpacked).
if (reg->array_dimensions() > name_tail.index.size()) {
cerr << get_fileline() << ": error: Cannot assign to array "

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@ -1800,7 +1800,7 @@ extern int ivl_scope_time_units(ivl_scope_t net);
* dimension.
*
* The ivl_signal_msb/ivl_signal_lsb functions are deprecated
* versions that only work with variables that have less then two
* versions that only work with variables that have less than two
* dimensions. They will return msb==lsb==0 for scalars.
*
* ivl_signal_port

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@ -4,7 +4,7 @@
%{
/*
* Copyright (c) 1998-2011 Stephen Williams (steve@icarus.com)
* Copyright (c) 1998-2012 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@ -309,7 +309,7 @@ TU [munpf]
}
}
/* If this identifer names a previously declared type, then
/* If this identifier names a previously declared type, then
return this as a TYPE_IDENTIFIER instead. */
if (rc == IDENTIFIER && gn_system_verilog()) {
if (data_type_t*type = pform_test_type_identifier(yylval.text)) {
@ -377,8 +377,11 @@ TU [munpf]
<< "Using SystemVerilog 'N bit vector. Use at least "
<< "-g2005-sv to remove this warning." << endl;
}
generation_t generation_save = generation_flag;
generation_flag = GN_VER2005_SV;
yylval.number = make_unsized_binary(yytext);
return BASED_NUMBER; }
generation_flag = generation_save;
return UNBASED_NUMBER; }
[0-9][0-9_]* {
yylval.number = make_unsized_dec(yytext);

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@ -130,7 +130,7 @@ extern NetExpr *normalize_variable_part_base(const list<long>&indices, NetExpr*b
unsigned long wid, bool is_up);
/*
* Calculate a canonicalizing expression for a slice select. The
* indices array is less then needed to fully address a bit, so the
* indices array is less than needed to fully address a bit, so the
* result is a slice of the packed array. The return value is an
* expression that gets to the base of the slice, and (lwid) becomes
* the width of the slice, in bits. For example:

10
parse.y
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@ -399,7 +399,7 @@ static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>
%token <data_type> TYPE_IDENTIFIER
%token <discipline> DISCIPLINE_IDENTIFIER
%token <text> PATHPULSE_IDENTIFIER
%token <number> BASED_NUMBER DEC_NUMBER
%token <number> BASED_NUMBER DEC_NUMBER UNBASED_NUMBER
%token <realtime> REALTIME
%token K_PLUS_EQ K_MINUS_EQ K_INCR K_DECR
%token K_LE K_GE K_EG K_EQ K_NE K_CEQ K_CNE K_LP K_LS K_RS K_RSS K_SG
@ -686,7 +686,7 @@ class_identifier
;
/* The endname after a class declaration is a little tricky because
the class name is detected by the lexor as a TYPE_IDENTIFER if it
the class name is detected by the lexor as a TYPE_IDENTIFIER if it
does indeed match a name. */
class_declaration_endname_opt
: ':' TYPE_IDENTIFIER
@ -1245,6 +1245,12 @@ number : BASED_NUMBER
| DEC_NUMBER BASED_NUMBER
{ $$ = pform_verinum_with_size($1,$2, @2.text, @2.first_line);
based_size = 0; }
| UNBASED_NUMBER
{ $$ = $1; based_size = 0;}
| DEC_NUMBER UNBASED_NUMBER
{ yyerror(@1, "error: Unbased SystemVerilog literal cannot have "
"a size.");
$$ = $1; based_size = 0;}
;
open_range_list /* IEEE1800-2005 A.2.11 */

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@ -403,7 +403,7 @@ extern svector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
/*
* The parser uses this function to convert a unary
* increment/decrement expression to the equivilent compressed
* increment/decrement expression to the equivalent compressed
* assignment statement.
*/
extern PAssign* pform_compressed_assign_from_inc_dec(const struct vlltype&loc,