Merge branch 'master' of github.com:steveicarus/iverilog
This commit is contained in:
commit
e55af496e5
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@ -200,7 +200,7 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
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// Special case: The l-value is an entire memory, or array
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// slice. This is, in fact, an error in l-values. Detect the
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// situation by noting if the index count is less then the
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// situation by noting if the index count is less than the
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// array dimensions (unpacked).
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if (reg->array_dimensions() > name_tail.index.size()) {
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cerr << get_fileline() << ": error: Cannot assign to array "
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@ -1800,7 +1800,7 @@ extern int ivl_scope_time_units(ivl_scope_t net);
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* dimension.
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*
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* The ivl_signal_msb/ivl_signal_lsb functions are deprecated
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* versions that only work with variables that have less then two
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* versions that only work with variables that have less than two
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* dimensions. They will return msb==lsb==0 for scalars.
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*
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* ivl_signal_port
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@ -4,7 +4,7 @@
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%{
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/*
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* Copyright (c) 1998-2011 Stephen Williams (steve@icarus.com)
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* Copyright (c) 1998-2012 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -309,7 +309,7 @@ TU [munpf]
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}
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}
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/* If this identifer names a previously declared type, then
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/* If this identifier names a previously declared type, then
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return this as a TYPE_IDENTIFIER instead. */
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if (rc == IDENTIFIER && gn_system_verilog()) {
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if (data_type_t*type = pform_test_type_identifier(yylval.text)) {
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@ -377,8 +377,11 @@ TU [munpf]
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<< "Using SystemVerilog 'N bit vector. Use at least "
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<< "-g2005-sv to remove this warning." << endl;
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}
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generation_t generation_save = generation_flag;
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generation_flag = GN_VER2005_SV;
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yylval.number = make_unsized_binary(yytext);
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return BASED_NUMBER; }
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generation_flag = generation_save;
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return UNBASED_NUMBER; }
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[0-9][0-9_]* {
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yylval.number = make_unsized_dec(yytext);
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@ -130,7 +130,7 @@ extern NetExpr *normalize_variable_part_base(const list<long>&indices, NetExpr*b
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unsigned long wid, bool is_up);
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/*
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* Calculate a canonicalizing expression for a slice select. The
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* indices array is less then needed to fully address a bit, so the
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* indices array is less than needed to fully address a bit, so the
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* result is a slice of the packed array. The return value is an
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* expression that gets to the base of the slice, and (lwid) becomes
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* the width of the slice, in bits. For example:
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10
parse.y
10
parse.y
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@ -399,7 +399,7 @@ static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>
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%token <data_type> TYPE_IDENTIFIER
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%token <discipline> DISCIPLINE_IDENTIFIER
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%token <text> PATHPULSE_IDENTIFIER
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%token <number> BASED_NUMBER DEC_NUMBER
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%token <number> BASED_NUMBER DEC_NUMBER UNBASED_NUMBER
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%token <realtime> REALTIME
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%token K_PLUS_EQ K_MINUS_EQ K_INCR K_DECR
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%token K_LE K_GE K_EG K_EQ K_NE K_CEQ K_CNE K_LP K_LS K_RS K_RSS K_SG
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@ -686,7 +686,7 @@ class_identifier
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;
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/* The endname after a class declaration is a little tricky because
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the class name is detected by the lexor as a TYPE_IDENTIFER if it
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the class name is detected by the lexor as a TYPE_IDENTIFIER if it
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does indeed match a name. */
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class_declaration_endname_opt
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: ':' TYPE_IDENTIFIER
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@ -1245,6 +1245,12 @@ number : BASED_NUMBER
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| DEC_NUMBER BASED_NUMBER
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{ $$ = pform_verinum_with_size($1,$2, @2.text, @2.first_line);
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based_size = 0; }
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| UNBASED_NUMBER
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{ $$ = $1; based_size = 0;}
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| DEC_NUMBER UNBASED_NUMBER
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{ yyerror(@1, "error: Unbased SystemVerilog literal cannot have "
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"a size.");
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$$ = $1; based_size = 0;}
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;
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open_range_list /* IEEE1800-2005 A.2.11 */
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2
pform.h
2
pform.h
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@ -403,7 +403,7 @@ extern svector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
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/*
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* The parser uses this function to convert a unary
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* increment/decrement expression to the equivilent compressed
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* increment/decrement expression to the equivalent compressed
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* assignment statement.
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*/
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extern PAssign* pform_compressed_assign_from_inc_dec(const struct vlltype&loc,
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