synthesis of Logic and shifts using vector gates.
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steve
parent
d0ade1d082
commit
3bd09d1470
147
expr_synth.cc
147
expr_synth.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: expr_synth.cc,v 1.68 2005/05/06 00:25:13 steve Exp $"
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#ident "$Id: expr_synth.cc,v 1.69 2005/05/15 04:47:00 steve Exp $"
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#endif
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# include "config.h"
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@ -92,73 +92,53 @@ NetNet* NetEBBits::synthesize(Design*des)
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assert(scope);
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string path = des->local_symbol(scope->name());
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if (lsig->pin_count() != rsig->pin_count()) {
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if (lsig->vector_width() != rsig->vector_width()) {
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cerr << get_line() << ": internal error: bitwise (" << op_
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<< ") widths do not match: " << lsig->pin_count()
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<< " != " << rsig->pin_count() << endl;
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<< ") widths do not match: " << lsig->vector_width()
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<< " != " << rsig->vector_width() << endl;
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cerr << get_line() << ": : width="
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<< lsig->pin_count() << ": " << *left_ << endl;
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<< lsig->vector_width() << ": " << *left_ << endl;
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cerr << get_line() << ": : width="
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<< rsig->pin_count() << ": " << *right_ << endl;
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<< rsig->vector_width() << ": " << *right_ << endl;
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return 0;
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}
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assert(lsig->pin_count() == rsig->pin_count());
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assert(lsig->vector_width() == rsig->vector_width());
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NetNet*osig = new NetNet(scope, scope->local_symbol(),
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NetNet::IMPLICIT, lsig->pin_count());
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NetNet::IMPLICIT, lsig->vector_width());
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osig->local_flag(true);
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for (unsigned idx = 0 ; idx < osig->pin_count() ; idx += 1) {
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perm_string oname = scope->local_symbol();
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NetLogic*gate;
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perm_string oname = scope->local_symbol();
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unsigned wid = lsig->vector_width();
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NetLogic*gate;
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/* If the rsig bit is constant, then look for special
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cases that I can use to reduce the generated
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logic. If I find one, then handle it immediately and
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skip the rest of the processing of this bit. */
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if (rsig->pin(idx).nexus()->drivers_constant()) {
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verinum::V bval = rsig->pin(idx).nexus()->driven_value();
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/* (A & 0) is (0) */
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if ((op() == '&') && bval == verinum::V0) {
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connect(osig->pin(idx), rsig->pin(idx));
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continue;
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}
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/* (A & 1) is A */
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if ((op() == '&') && bval == verinum::V1) {
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connect(osig->pin(idx), lsig->pin(idx));
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continue;
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}
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}
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switch (op()) {
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case '&':
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gate = new NetLogic(scope, oname, 3, NetLogic::AND, 1);
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break;
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case '|':
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gate = new NetLogic(scope, oname, 3, NetLogic::OR, 1);
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break;
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case '^':
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gate = new NetLogic(scope, oname, 3, NetLogic::XOR, 1);
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break;
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case 'O':
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gate = new NetLogic(scope, oname, 3, NetLogic::NOR, 1);
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break;
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case 'X':
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gate = new NetLogic(scope, oname, 3, NetLogic::XNOR, 1);
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break;
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default:
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assert(0);
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}
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connect(osig->pin(idx), gate->pin(0));
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connect(lsig->pin(idx), gate->pin(1));
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connect(rsig->pin(idx), gate->pin(2));
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des->add_node(gate);
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switch (op()) {
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case '&':
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gate = new NetLogic(scope, oname, 3, NetLogic::AND, wid);
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break;
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case '|':
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gate = new NetLogic(scope, oname, 3, NetLogic::OR, wid);
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break;
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case '^':
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gate = new NetLogic(scope, oname, 3, NetLogic::XOR, wid);
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break;
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case 'O':
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gate = new NetLogic(scope, oname, 3, NetLogic::NOR, wid);
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break;
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case 'X':
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gate = new NetLogic(scope, oname, 3, NetLogic::XNOR, wid);
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break;
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default:
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assert(0);
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}
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connect(osig->pin(0), gate->pin(0));
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connect(lsig->pin(0), gate->pin(1));
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connect(rsig->pin(0), gate->pin(2));
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gate->set_line(*this);
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des->add_node(gate);
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return osig;
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}
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@ -518,30 +498,40 @@ NetNet* NetEBShift::synthesize(Design*des)
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NetNet::IMPLICIT, expr_width());
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osig->local_flag(true);
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NetConst*zcon = new NetConst(scope, scope->local_symbol(),
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verinum::V0);
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des->add_node(zcon);
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NetNet*zsig = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, 1);
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connect(zcon->pin(0), zsig->pin(0));
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unsigned long ushift = shift>=0? shift : -shift;
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if (ushift > osig->vector_width())
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ushift = osig->vector_width();
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if (shift > 0) {
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unsigned long ushift = shift;
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for (unsigned idx = 0; idx < osig->pin_count(); idx += 1)
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if (idx < ushift) {
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connect(osig->pin(idx), zsig->pin(0));
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} else {
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connect(osig->pin(idx), lsig->pin(idx-ushift));
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}
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} else {
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unsigned long dshift = 0-shift;
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for (unsigned idx = 0; idx < osig->pin_count() ; idx += 1)
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if (idx+dshift < lsig->pin_count())
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connect(osig->pin(idx), lsig->pin(idx+dshift));
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else
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connect(osig->pin(idx), zsig->pin(0));
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verinum znum (verinum::V0, ushift, true);
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NetConst*zcon = new NetConst(scope, scope->local_symbol(),
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znum);
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des->add_node(zcon);
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/* Detect the special case that the shift is the size of
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the whole expression. Simply connect the pad to the
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osig and escape. */
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if (ushift >= osig->vector_width()) {
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connect(zcon->pin(0), osig->pin(0));
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return osig;
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}
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NetNet*zsig = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, znum.len());
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connect(zcon->pin(0), zsig->pin(0));
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NetConcat*ccat = new NetConcat(scope, scope->local_symbol(),
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osig->vector_width(), 2);
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ccat->set_line(*this);
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des->add_node(ccat);
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connect(ccat->pin(0), osig->pin(0));
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if (shift > 0) {
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connect(ccat->pin(1), zsig->pin(0));
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connect(ccat->pin(2), lsig->pin(0));
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} else {
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connect(ccat->pin(1), lsig->pin(0));
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connect(ccat->pin(2), zsig->pin(0));
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}
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return osig;
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}
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@ -837,6 +827,9 @@ NetNet* NetESignal::synthesize(Design*des)
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/*
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* $Log: expr_synth.cc,v $
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* Revision 1.69 2005/05/15 04:47:00 steve
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* synthesis of Logic and shifts using vector gates.
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*
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* Revision 1.68 2005/05/06 00:25:13 steve
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* Handle synthesis of concatenation expressions.
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*
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