Add regression test for issue #703.

This commit is contained in:
Martin Whitaker 2024-02-09 22:38:32 +00:00
parent 855dd3a7e6
commit 72e86d396c
3 changed files with 50 additions and 0 deletions

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@ -0,0 +1,44 @@
module test;
logic [7:0] dout;
logic [7:0] sel;
for (genvar i = 0; i < 8; i++) begin
if (i == 0) begin
assign dout[i] = 1'b0;
end else if (i == 1) begin
assign dout[i] = 1'b1;
end else begin
// using always block reports error
always @(*) begin
if (sel[i]) dout[i] = 1'b1;
else dout[i] = 1'b0;
end
end
end
logic [7:0] expected;
reg failed = 0;
initial begin
sel = 8'd1;
repeat (8) begin
#1 $display("%b %b", sel, dout);
expected = sel & 8'b11111100 | 8'b00000010;
if (dout !== expected) failed = 1;
sel = sel << 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule

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@ -27,6 +27,7 @@ br_gh383d vvp_tests/br_gh383d.json
br_gh440 vvp_tests/br_gh440.json
br_gh552 vvp_tests/br_gh552.json
br_gh687 vvp_tests/br_gh687.json
br_gh703 vvp_tests/br_gh703.json
br_gh710a vvp_tests/br_gh710a.json
br_gh710b vvp_tests/br_gh710b.json
br_gh710c vvp_tests/br_gh710c.json

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{
"type" : "normal",
"source" : "br_gh703.v",
"iverilog-args" : [ "-g2009" ]
}