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Initialize all range variables in the constructor to avoid false asserts. 

This would have never been a problem with the actual circuit generated.
The problem was that the assert was checking values that had never been
set. The constructor now explicitly sets these values to zero and while
I was at it I added a couple more asserts.
This commit is contained in:
Cary R 2007-08-22 09:16:34 -07:00 committed by Stephen Williams
parent b69c4c9a2c
commit 35df445db1
2 changed files with 6 additions and 1 deletions
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3
PWire.cc
View File

@ -31,7 +31,8 @@ PWire::PWire(const pform_name_t&n,
ivl_variable_type_t dt)
: hname_(n), type_(t), port_type_(pt), data_type_(dt),
signed_(false), isint_(false), port_set_(false), net_set_(false),
error_cnt_(0), lidx_(0), ridx_(0)
port_msb_(0), port_lsb_(0), net_msb_(0), net_lsb_(0), error_cnt_(0),
lidx_(0), ridx_(0)
{
if (t == NetNet::INTEGER) {
type_ = NetNet::REG;

4
elab_sig.cc
View File

@ -592,7 +592,9 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
nmsb = pmsb;
nlsb = plsb;
}
if (!port_set_) assert(port_msb_ == 0 && port_lsb_ == 0);
if (port_msb_ == 0) assert(port_lsb_ == 0);
if (port_lsb_ == 0) assert(port_msb_ == 0);
/* If they exist get the net/etc. definition MSB and LSB */
if (net_set_ && net_msb_ != 0) {
@ -620,7 +622,9 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
delete texpr;
}
if (!net_set_) assert(net_msb_ == 0 && net_lsb_ == 0);
if (net_msb_ == 0) assert(net_lsb_ == 0);
if (net_lsb_ == 0) assert(net_msb_ == 0);
/* We have a port size error */
if (port_set_ && net_set_ && (pmsb != nmsb || plsb != nlsb)) {