Support conversion of (un)signed to std_logic
Take the least-significant bit. This fixes a couple of broken test cases.
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331a51e842
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d21b3258e3
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@ -106,6 +106,28 @@ vhdl_expr *vhdl_expr::cast(const vhdl_type *to)
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return ah;
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}
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else if (to->get_name() == VHDL_TYPE_STD_LOGIC
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&& (type_->get_name() == VHDL_TYPE_SIGNED)) {
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require_support_function(SF_SIGNED_TO_LOGIC);
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vhdl_fcall *ah =
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new vhdl_fcall(support_function::function_name(SF_SIGNED_TO_LOGIC),
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vhdl_type::std_logic());
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ah->add_expr(this);
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return ah;
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}
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else if (to->get_name() == VHDL_TYPE_STD_LOGIC
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&& (type_->get_name() == VHDL_TYPE_UNSIGNED)) {
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require_support_function(SF_UNSIGNED_TO_LOGIC);
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vhdl_fcall *ah =
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new vhdl_fcall(support_function::function_name(SF_UNSIGNED_TO_LOGIC),
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vhdl_type::std_logic());
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ah->add_expr(this);
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return ah;
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}
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else {
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// We have to cast the expression before resizing or the
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// wrong sign bit may be extended (i.e. when casting between
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@ -44,6 +44,8 @@ const char *support_function::function_name(support_function_t type)
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case SF_TERNARY_UNSIGNED: return "Ternary_Unsigned";
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case SF_TERNARY_SIGNED: return "Ternary_Signed";
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case SF_LOGIC_TO_INTEGER: return "Logic_To_Integer";
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case SF_SIGNED_TO_LOGIC: return "Signed_To_Logic";
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case SF_UNSIGNED_TO_LOGIC: return "Unsigned_To_Logic";
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default:
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assert(false);
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}
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@ -60,6 +62,8 @@ vhdl_type *support_function::function_type(support_function_t type)
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case SF_REDUCE_AND:
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case SF_REDUCE_XOR:
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case SF_TERNARY_LOGIC:
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case SF_SIGNED_TO_LOGIC:
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case SF_UNSIGNED_TO_LOGIC:
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return vhdl_type::std_logic();
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case SF_TERNARY_SIGNED:
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return new vhdl_type(VHDL_TYPE_SIGNED);
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@ -102,6 +106,16 @@ void support_function::emit(std::ostream &of, int level) const
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<< "return '0';" << nl_string(indent(level))
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<< "end if;";
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break;
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case SF_UNSIGNED_TO_LOGIC:
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of << "(X : unsigned) return std_logic is" << nl_string(level)
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<< "begin" << nl_string(indent(level))
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<< "return X(0);";
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break;
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case SF_SIGNED_TO_LOGIC:
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of << "(X : signed) return std_logic is" << nl_string(level)
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<< "begin" << nl_string(indent(level))
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<< "return X(0);";
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break;
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case SF_REDUCE_OR:
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of << "(X : std_logic_vector) return std_logic is" << nl_string(level)
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<< "begin" << nl_string(indent(level))
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@ -34,6 +34,8 @@ enum support_function_t {
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SF_TERNARY_UNSIGNED,
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SF_TERNARY_SIGNED,
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SF_LOGIC_TO_INTEGER,
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SF_SIGNED_TO_LOGIC,
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SF_UNSIGNED_TO_LOGIC,
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};
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class support_function : public vhdl_function {
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