tgt-vvp: Add resize for string element assignment where necessary

There are some cases where during an assignment the elaboration step can
generate constructs with the right-hand-side expression being wider than
the left-hand-side expression.

To handle this the tgt-vvp backend inserts a %pad operation when necessary.
One place where this is missing is when writing to an string element. Here
instead an assert is triggered requiring the right-hand-side expression to
be 8 bits wide.

E.g.
```
bit [7:0] x;
bit [8:0] y;
string s;

x = y; // tgt-vvp inserts %pad
s[0] = y; // tgt-vvp triggers assert
```

Long term this should be fixed at the elaboration stage and insert the
proper width cast. But for now solve this the same way as other places in
tgt-vvp and insert the %pad operation for string element assignments if the
width does not match.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

tgt-vvp/stmt_assign.c

@@ -884,8 +884,8 @@ static int show_stmt_assign_sig_string(ivl_statement_t net)
 	    return 0;
       }
 
-      assert(ivl_expr_width(rval)==8);
       draw_eval_vec4(rval);
+      resize_vec4_wid(rval, 8);
 
 	/* Calculate the character select for the word. */
       int mux_word = allocate_word();