Remove useless comments in output
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17ae0a6a09
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@ -40,8 +40,8 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
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const char *type = ivl_process_type(proc) == IVL_PR_INITIAL
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? "initial" : "always";
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std::ostringstream ss;
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ss << "Generated from " << type << " process in scope ";
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ss << ivl_scope_name(scope);
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ss << "Generated from " << type << " process in ";
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ss << ivl_scope_tname(scope);
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vhdl_proc->set_comment(ss.str());
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// Store it in the entity's architecture
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@ -48,9 +48,7 @@ static vhdl_entity *create_entity_for(ivl_scope_t scope)
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// Build a comment to add to the entity/architecture
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std::ostringstream ss;
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ss << "Generated from " << ivl_scope_name(scope);
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ss << " (" << ivl_scope_def_file(scope) << ":";
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ss << ivl_scope_def_lineno(scope) << ")";
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ss << "Generated from Verilog module " << ivl_scope_tname(scope);
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arch->set_comment(ss.str());
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ent->set_comment(ss.str());
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@ -97,10 +95,8 @@ static int draw_module(ivl_scope_t scope, ivl_scope_t parent)
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// And an instantiation statement
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const char *inst_name = ivl_scope_basename(scope);
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vhdl_comp_inst *inst = new vhdl_comp_inst(inst_name, ent->get_name().c_str());
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std::ostringstream ss;
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ss << "Generated from " << ivl_scope_name(scope);
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inst->set_comment(ss.str());
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vhdl_comp_inst *inst =
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new vhdl_comp_inst(inst_name, ent->get_name().c_str());
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parent_arch->add_stmt(inst);
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}
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else {
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@ -208,7 +208,7 @@ void vhdl_process::emit(std::ofstream &of, int level) const
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of << "begin";
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newline(of, level);
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// ...statements...
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of << "wait;"; // Just to stop the simulation hanging
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of << " wait;"; // Just to stop the simulation hanging
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newline(of, level);
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of << "end process;";
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newline(of, level);
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