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Recover from port and signal vector range mismatch 

When using non-ANSI style port declarations it is possible to have both a
port and net or variable declaration for the same signal. In this case the
range specification for the two declarations have to match.

In the current implementation if the range specifications do not match an
error is reported and no signal is created. This generates follow up errors
about the signal not being declared when it is used.

In some cases it even causes the application to crash. E.g. the task
elaboration expects the port signal to exist. If it does not it will crash.

To avoid this still create the signal, even when an error is detected. Use
the range specification of the net or variable in this case. Overall
elaboration will still fail due to the error, but the application will not
crash.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2022-03-12 11:11:43 +01:00
parent ede341410f
commit 0328fc5a6f
1 changed files with 0 additions and 3 deletions
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3
elab_sig.cc
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@ -1042,7 +1042,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
<< "'' has a vectored net declaration "
<< nlist << "." << endl;
des->errors += 1;
return 0;
}
}
@ -1054,7 +1053,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
<< " has a scalar net declaration at "
<< get_fileline() << "." << endl;
des->errors += 1;
return 0;
}
/* Both vectored, but they have different ranges. */
@ -1066,7 +1064,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
<< " at " << net_.front().first->get_fileline()
<< " that does not match." << endl;
des->errors += 1;
return 0;
}
}