Merge pull request #961 from larsclausen/fix-bitsel-sign

Fix bit select on signed multi-dimensional packed array

elab_expr.cc

@@ -4321,12 +4321,7 @@ unsigned PEIdent::test_width(Design*des, NetScope*scope, width_mode_t&mode)
 		const index_component_t&index_tail = name_tail.index.back();
 		ivl_assert(*this, index_tail.msb);
 	      }
-		// If we have a net in hand, then we can predict what the
-		// slice width will be. If not, then assume it will be a
-		// simple bit select. If the net only has a single dimension
-		// then this is still a simple bit select.
-	      if ((sr.net == 0) || (sr.net->packed_dimensions() <= 1))
-		    use_width = 1;
+	      use_width = 1;
 	      break;
 	  case index_component_t::SEL_BIT_LAST:
 	    if (debug_elaborate) {

ivtest/ivltests/bitsel11.v

@@ -0,0 +1,63 @@
+// Check that element and bit select on multi-dimensional signed packed arrays
+// are unsigned.
+
+module test;
+
+  bit failed = 1'b0;
+
+`define check(val, exp) do begin \
+    if (val !== exp) begin \
+      $display("FAILED(%0d): Expected `%b`, got `%b`.", `__LINE__, exp, val); \
+      failed = 1'b1; \
+    end \
+  end while (0)
+
+  reg signed [3:0][3:0] arr;
+  integer idx;
+  reg [7:0] x;
+  reg [3:0] y;
+  reg [31:0] z;
+
+  initial begin
+    // Set lowest element to all 1
+    arr = 16'hffff;
+
+    // Elements of a signed packed array are unsigned, no sign extensions
+    idx = 0;
+    x = arr[idx];
+    `check(x, 8'h0f);
+
+    // Out-of-bounds
+    idx = -1;
+    x = arr[idx];
+    `check(x, 8'h0x);
+
+    // Undefined
+    idx = 'bx;
+    x = arr[idx];
+    `check(x, 8'h0x);
+
+    // Bit selects on a signed packed array are unsigned, no sign extensions
+    idx = 0;
+    y = arr[0][idx];
+    `check(y, 4'b0001);
+
+    // Out-of-bounds
+    idx = -1;
+    y = arr[0][idx];
+    `check(y, 4'b000x);
+
+    // Undefined
+    idx = 'bx;
+    y = arr[0][idx];
+    `check(y, 4'b000x);
+
+    // The array as a primary is signed, sign extension
+    z = arr;
+    `check(z, 32'hffffffff);
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+endmodule

ivtest/regress-vvp.list

@@ -3,6 +3,7 @@
 # describes the test.
 
 array_packed_write_read		vvp_tests/array_packed_write_read.json
+bitsel11			vvp_tests/bitsel11.json
 br_gh13a			vvp_tests/br_gh13a.json
 br_gh13a-vlog95			vvp_tests/br_gh13a-vlog95.json
 br_gh939			vvp_tests/br_gh939.json

ivtest/vvp_tests/bitsel11.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "bitsel11.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}