Spelling fixes

No code changes.

driver/main.c

@@ -929,7 +929,7 @@ int main(int argc, char **argv)
 	/* Done writing to the iconfig file. Close it now. */
       fclose(iconfig_file);
 
-	/* If we're only here for th verion output, then we're done. */
+	/* If we're only here for the version output, then we're done. */
       if (version_flag)
 	    return t_version_only();
 

pform_disciplines.cc

@@ -78,7 +78,7 @@ void pform_end_nature(const struct vlltype&loc)
 	    error_count += 1;
       }
 
-	// Map the access functio back to the nature so that
+	// Map the access function back to the nature so that
 	// expressions that use the access function can find it.
       access_function_nature[nature_access] = tmp;
 

tgt-vhdl/logic.cc

@@ -47,7 +47,7 @@ static vhdl_expr *inputs_to_expr(vhdl_scope *scope, vhdl_binop_t op,
 }
 
 /*
- * Convert a gate intput to an unary expression.
+ * Convert a gate input to an unary expression.
  */
 static vhdl_expr *input_to_expr(vhdl_scope *scope, vhdl_unaryop_t op,
                                 ivl_net_logic_t log)

tgt-vhdl/stmt.cc

@@ -34,7 +34,7 @@
  * successfully.
  *
  * An alternative is to use the VHPI interface supported by
- * some VHDL simulators and implement the $finish funcitonality
+ * some VHDL simulators and implement the $finish functionality
  * in C. This function can be enabled with the flag
  * -puse-vhpi-finish=1. 
  */
@@ -226,12 +226,12 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container,
       // performed on assignments of constant values to prevent
       // ordering problems.
       
-      // This also has another application: If this is an `inital'
+      // This also has another application: If this is an `initial'
       // process and we haven't yet generated a `wait' statement then
       // moving the assignment to the initialization preserves the
       // expected Verilog behaviour: VHDL does not distinguish
       // `initial' and `always' processes so an `always' process might
-      // be activatated before an `initial' process at time 0. The
+      // be activated before an `initial' process at time 0. The
       // `always' process may then use the uninitialized signal value.
       // The second test ensures that we only try to initialise
       // internal signals not ports
@@ -622,7 +622,7 @@ int draw_utask(vhdl_procedural *proc, stmt_container *container,
 
    // TODO: adding some comments to the output would be helpful
 
-   // TOOD: this completely ignores paremeters!
+   // TOOD: this completely ignores parameters!
    draw_stmt(proc, container, ivl_scope_def(tscope), false);
    
    return 0;

tgt-vhdl/vhdl.cc

@@ -97,7 +97,7 @@ bool seen_signal_before(ivl_signal_t sig)
 }
 
 /*
- * Remeber the association of signal to entity.
+ * Remember the association of signal to entity.
  */
 void remember_signal(ivl_signal_t sig, vhdl_scope *scope)
 {

tgt-vhdl/vhdl_syntax.cc

@@ -854,7 +854,7 @@ vhdl_function::vhdl_function(const char *name, vhdl_type *ret_type)
    : vhdl_decl(name, ret_type)
 {
    // A function contains two scopes:
-   //  scope_ = The paramters
+   //  scope_ = The parameters
    //  variables_ = Local variables
    // A call to get_scope returns variables_ whose parent is scope_
    variables_.set_parent(&scope_);