Merge pull request #1201 from larsclausen/nested-lvalue-types
tgt-vvp: Support nested lvalues for all property types
This commit is contained in:
commit
27bae7eab1
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@ -0,0 +1,40 @@
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// Check that nested dynamic array typed class properties can be used as
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// lvalues.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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class C;
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C c;
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int d[];
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endclass
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initial begin
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C c1, c2;
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int d[];
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c1 = new;
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c1.c = new;
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c2 = c1.c;
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d = new[2];
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d[0] = 10;
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c1.c.d = d;
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d = c2.d;
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`check(d[0], 10);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,38 @@
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// Check that nested object typed class properties can be used as lvalues.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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class C;
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C c;
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integer i;
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endclass
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initial begin
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C c1, c2, c3;
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c1 = new;
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c1.c = new;
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c2 = c1.c;
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c3 = new;
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c3.i = 10;
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c1.c.c = c3;
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c3 = c2.c;
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`check(c3.i, 10);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,34 @@
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// Check that nested real typed class properties can be used as lvalues.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val != exp) begin \
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$display("FAILED(%0d). '%s' expected %f, got %f", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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class C;
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C c;
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real r;
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endclass
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initial begin
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C c1, c2;
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c1 = new;
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c1.c = new;
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c2 = c1.c;
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c1.c.r = 12.3;
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`check(c2.r, 12.3);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,34 @@
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// Check that nested string typed class properties can be used as lvalues.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val != exp) begin \
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$display("FAILED(%0d). '%s' expected %s, got %s", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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class C;
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C c;
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string s;
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endclass
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initial begin
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C c1, c2;
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c1 = new;
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c1.c = new;
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c2 = c1.c;
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c1.c.s = "Hello";
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`check(c2.s, "Hello");
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,34 @@
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// Check that nested vector typed class properties can be used as lvalues.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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class C;
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C c;
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int i;
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endclass
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initial begin
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C c1, c2;
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c1 = new;
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c1.c = new;
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c2 = c1.c;
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c1.c.i = 10;
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`check(c2.i, 10);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -225,6 +225,11 @@ sv_chained_constructor5 vvp_tests/sv_chained_constructor5.json
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sv_class_prop_assign_op1 vvp_tests/sv_class_prop_assign_op1.json
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sv_class_prop_assign_op2 vvp_tests/sv_class_prop_assign_op2.json
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sv_class_prop_logic vvp_tests/sv_class_prop_logic.json
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sv_class_prop_nest_darray1 vvp_tests/sv_class_prop_nest_darray1.json
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sv_class_prop_nest_obj1 vvp_tests/sv_class_prop_nest_obj1.json
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sv_class_prop_nest_real1 vvp_tests/sv_class_prop_nest_str1.json
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sv_class_prop_nest_str1 vvp_tests/sv_class_prop_nest_real1.json
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sv_class_prop_nest_vec1 vvp_tests/sv_class_prop_nest_vec1.json
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sv_const1 vvp_tests/sv_const1.json
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sv_const2 vvp_tests/sv_const2.json
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sv_const3 vvp_tests/sv_const3.json
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@ -0,0 +1,5 @@
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{
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"type" : "normal",
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"source" : "sv_class_prop_nest_darray1.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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@ -0,0 +1,5 @@
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{
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"type" : "normal",
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"source" : "sv_class_prop_nest_obj1.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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@ -0,0 +1,5 @@
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{
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"type" : "normal",
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"source" : "sv_class_prop_nest_real1.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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@ -0,0 +1,5 @@
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{
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"type" : "normal",
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"source" : "sv_class_prop_nest_str1.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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@ -0,0 +1,5 @@
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{
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"type" : "normal",
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"source" : "sv_class_prop_nest_vec1.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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@ -371,25 +371,27 @@ static ivl_type_t draw_lval_expr(ivl_lval_t lval)
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{
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ivl_lval_t lval_nest = ivl_lval_nest(lval);
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ivl_signal_t lval_sig = ivl_lval_sig(lval);
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ivl_type_t sub_type;
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if (lval_nest) {
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sub_type = draw_lval_expr(lval_nest);
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} else {
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assert(lval_sig);
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sub_type = ivl_signal_net_type(lval_sig);
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assert(ivl_type_base(sub_type) == IVL_VT_CLASS);
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if (lval_sig) {
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fprintf(vvp_out, " %%load/obj v%p_0;\n", lval_sig);
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return ivl_signal_net_type(lval_sig);
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}
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assert (lval_nest);
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ivl_type_t sub_type = draw_lval_expr(lval_nest);
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assert(ivl_type_base(sub_type) == IVL_VT_CLASS);
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if (ivl_lval_idx(lval)) {
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if (ivl_lval_idx(lval_nest)) {
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fprintf(vvp_out, " ; XXXX Don't know how to handle ivl_lval_idx values here.\n");
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}
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fprintf(vvp_out, " %%prop/obj %d, 0; draw_lval_expr\n", ivl_lval_property_idx(lval));
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int prop_idx = ivl_lval_property_idx(lval_nest);
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fprintf(vvp_out, " %%prop/obj %d, 0; Load property %s\n", prop_idx,
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ivl_type_prop_name(sub_type, prop_idx));
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fprintf(vvp_out, " %%pop/obj 1, 1;\n");
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return ivl_type_prop_type(sub_type, ivl_lval_property_idx(lval));
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return ivl_type_prop_type(sub_type, prop_idx);
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}
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/*
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@ -407,7 +409,6 @@ static void store_vec4_to_lval(ivl_statement_t net)
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for (unsigned lidx = 0 ; lidx < ivl_stmt_lvals(net) ; lidx += 1) {
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ivl_lval_t lval = ivl_stmt_lval(net,lidx);
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ivl_signal_t lsig = ivl_lval_sig(lval);
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ivl_lval_t nest = ivl_lval_nest(lval);
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unsigned lwid = ivl_lval_width(lval);
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@ -461,19 +462,6 @@ static void store_vec4_to_lval(ivl_statement_t net)
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}
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clr_word(offset_index);
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} else if (nest) {
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/* No offset expression, but the l-value is
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nested, which probably means that it is a class
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member. We will use a property assign
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function. */
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assert(!lsig);
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ivl_type_t sub_type = draw_lval_expr(nest);
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assert(ivl_type_base(sub_type) == IVL_VT_CLASS);
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fprintf(vvp_out, " %%store/prop/v %d, %u;\n",
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ivl_lval_property_idx(lval), lwid);
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fprintf(vvp_out, " %%pop/obj 1, 0;\n");
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} else {
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/* No offset expression, so use simpler store function. */
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assert(lsig);
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@ -1321,16 +1309,13 @@ static int show_stmt_assign_sig_cobject(ivl_statement_t net)
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int errors = 0;
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ivl_lval_t lval = ivl_stmt_lval(net, 0);
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ivl_expr_t rval = ivl_stmt_rval(net);
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ivl_signal_t sig= ivl_lval_sig(lval);
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unsigned lwid = ivl_lval_width(lval);
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int prop_idx = ivl_lval_property_idx(lval);
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if (prop_idx >= 0) {
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ivl_type_t sig_type = ivl_signal_net_type(sig);
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ivl_type_t prop_type = ivl_type_prop_type(sig_type, prop_idx);
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fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
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if (prop_idx >= 0) {
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ivl_type_t sig_type = draw_lval_expr(lval);
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ivl_type_t prop_type = ivl_type_prop_type(sig_type, prop_idx);
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if (ivl_type_base(prop_type) == IVL_VT_BOOL ||
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ivl_type_base(prop_type) == IVL_VT_LOGIC) {
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@ -1413,6 +1398,9 @@ static int show_stmt_assign_sig_cobject(ivl_statement_t net)
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}
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} else {
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ivl_signal_t sig = ivl_lval_sig(lval);
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assert(!ivl_lval_nest(lval));
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if (ivl_expr_type(rval) == IVL_EX_ARRAY_PATTERN) {
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draw_array_pattern(sig, rval, 0);
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return 0;
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@ -1466,7 +1454,8 @@ int show_stmt_assign(ivl_statement_t net)
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return show_stmt_assign_sig_queue(net);
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}
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if (sig && (ivl_signal_data_type(sig) == IVL_VT_CLASS)) {
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if ((sig && (ivl_signal_data_type(sig) == IVL_VT_CLASS)) ||
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ivl_lval_nest(lval)) {
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return show_stmt_assign_sig_cobject(net);
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}
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