luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Types of task/function arguments set in multiple steps.

This commit is contained in:
steve 2007-01-29 02:07:34 +00:00
parent d175eb17f1
commit cfe2198e5e
2 changed files with 22 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
elab_sig.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: elab_sig.cc,v 1.43 2007/01/16 05:44:15 steve Exp $"
#ident "$Id: elab_sig.cc,v 1.44 2007/01/29 02:07:34 steve Exp $"
#endif
# include "config.h"
@ -703,7 +703,19 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
NetNet*sig = new NetNet(scope, name, wtype, msb, lsb,
array_s0, array_e0);
sig->data_type(data_type_);
ivl_variable_type_t use_data_type = data_type_;
if (use_data_type == IVL_VT_NO_TYPE) {
use_data_type = IVL_VT_LOGIC;
if (debug_elaborate) {
cerr << get_line() << ": debug: "
<< "Signal " << name
<< " in scope " << scope->name()
<< " defaults to data type " << use_data_type << endl;
}
}
sig->data_type(use_data_type);
sig->set_line(*this);
sig->port_type(port_type_);
sig->set_signed(get_signed());
@ -718,6 +730,9 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
/*
* $Log: elab_sig.cc,v $
* Revision 1.44 2007/01/29 02:07:34 steve
* Types of task/function arguments set in multiple steps.
*
* Revision 1.43 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory

9
parse.y
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: parse.y,v 1.224 2007/01/16 05:44:15 steve Exp $"
#ident "$Id: parse.y,v 1.225 2007/01/29 02:07:34 steve Exp $"
#endif
# include "config.h"
@ -1111,7 +1111,7 @@ function_item
: K_input signed_opt range_opt list_of_identifiers ';'
{ svector<PWire*>*tmp
= pform_make_task_ports(NetNet::PINPUT,
IVL_VT_LOGIC, $2,
IVL_VT_NO_TYPE, $2,
$3, $4,
@1.text, @1.first_line);
$$ = tmp;
@ -1119,7 +1119,7 @@ function_item
| K_output signed_opt range_opt list_of_identifiers ';'
{ svector<PWire*>*tmp
= pform_make_task_ports(NetNet::PINPUT,
IVL_VT_LOGIC, $2,
IVL_VT_NO_TYPE, $2,
$3, $4,
@1.text, @1.first_line);
$$ = tmp;
@ -1128,12 +1128,13 @@ function_item
| K_inout signed_opt range_opt list_of_identifiers ';'
{ svector<PWire*>*tmp
= pform_make_task_ports(NetNet::PINPUT,
IVL_VT_LOGIC, $2,
IVL_VT_NO_TYPE, $2,
$3, $4,
@1.text, @1.first_line);
$$ = tmp;
yyerror(@1, "Functions may not have inout ports.");
}
/* When the port is an integer, infer a signed vector of the integer
shape. Generate a range to make it work. */