luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Perform bit <-> real conversions for module inputs. 

This patch makes the compiler perform either bit to real or
real to bit conversion when needed on module input signals.
This commit is contained in:
Cary R 2010-03-24 19:28:28 -07:00 committed by Stephen Williams
parent bc7a5a9725
commit 8e69764834
1 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
elaborate.cc
View File

@ -1266,6 +1266,22 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
sig = tmp2;
}
// If we have a real signal driving a bit/vector port
// then we convert the real value using the appropriate
// width cast. Since a real is only one bit the whole
// thing needs to go to each instance when arrayed.
if ((sig->data_type() == IVL_VT_REAL ) &&
prts.size() && (prts[0]->data_type() != IVL_VT_REAL )) {
sig = cast_to_int(des, scope, sig,
prts_vector_width/instance.size());
}
// If we have a bit/vector signal driving a real port
// then we convert the value to a real.
if ((sig->data_type() != IVL_VT_REAL ) &&
prts.size() && (prts[0]->data_type() == IVL_VT_REAL )) {
sig = cast_to_real(des, scope, sig);
}
} else if (prts[0]->port_type() == NetNet::PINOUT) {
/* Inout to/from module. This is a more