Annotate the parse of simple concurrent statements.

vhdlpp/architec.cc

@@ -19,11 +19,29 @@
 
 # include  "architec.h"
 
-Architecture::Architecture(perm_string name)
+Architecture::Architecture(perm_string name, std::list<Architecture::Statement*>&s)
 : name_(name)
 {
+      statements_.splice(statements_.end(), s);
 }
 
 Architecture::~Architecture()
 {
 }
+
+Architecture::Statement::Statement()
+{
+}
+
+Architecture::Statement::~Statement()
+{
+}
+
+SignalAssignment::SignalAssignment(perm_string targ_name)
+: target_name_(targ_name)
+{
+}
+
+SignalAssignment::~SignalAssignment()
+{
+}

vhdlpp/architec.h

@@ -21,11 +21,35 @@
 
 # include  "StringHeap.h"
 # include  "LineInfo.h"
+# include  <list>
 
+/*
+ * The Architecture class carries the contents (name, statements,
+ * etc.) of a parsed VHDL architecture. These objects are ultimately
+ * put into entities.
+ */
 class Architecture : public LineInfo {
 
     public:
-      Architecture(perm_string name);
+	// Architectures contain concurrent statements, that are
+	// derived from this nested class.
+      class Statement : public LineInfo {
+
+	  public:
+	    Statement();
+	    virtual ~Statement() =0;
+
+	    virtual void dump(ostream&out) const;
+
+	  private:
+
+	  private: // Not implemented
+      };
+
+    public:
+	// Create an architecture from its name and its statements.
+	// NOTE: The statement list passed in is emptied.
+      Architecture(perm_string name, std::list<Architecture::Statement*>&s);
       ~Architecture();
 
       perm_string get_name() const { return name_; }
@@ -35,7 +59,25 @@ class Architecture : public LineInfo {
     private:
       perm_string name_;
 
+      std::list<Architecture::Statement*> statements_;
+
     private: // Not implemented
 };
 
+/*
+ * The SignalAssignment class represents the
+ * concurrent_signal_assignment that is placed in an architecture.
+ */
+class SignalAssignment  : public Architecture::Statement {
+
+    public:
+      SignalAssignment(perm_string target_name);
+      ~SignalAssignment();
+
+      virtual void dump(ostream&out) const;
+
+    private:
+      perm_string target_name_;
+};
+
 #endif

vhdlpp/debug.cc

@@ -80,4 +80,20 @@ void Architecture::dump(ostream&out, perm_string of_entity) const
       out << "architecture " << name_
 	  << " of entity " << of_entity
 	  << " file=" << get_fileline() << endl;
+
+      for (list<Architecture::Statement*>::const_iterator cur = statements_.begin()
+		 ; cur != statements_.end() ; ++cur) {
+	    (*cur)->dump(out);
+      }
+}
+
+void Architecture::Statement::dump(ostream&out) const
+{
+      out << "   Architecutre::Statement at file=" << get_fileline() << endl;
+}
+
+void SignalAssignment::dump(ostream&out) const
+{
+      out << "   SignalAssignment file=" << get_fileline() << endl;
+      out << "     " << target_name_ << " <= <expr>" << endl;
 }

vhdlpp/parse.y

@@ -51,6 +51,9 @@ int parse_errors = 0;
       
       InterfacePort*interface_element;
       std::list<InterfacePort*>* interface_list;
+
+      Architecture::Statement* arch_statement;
+      std::list<Architecture::Statement*>* arch_statement_list;
 };
 
   /* The keywords are all tokens. */
@@ -87,10 +90,14 @@ int parse_errors = 0;
 %token LEQ GEQ VASSIGN NE BOX EXP ARROW DLT DGT
 
  /* The rules may have types. */
+
 %type <interface_element> interface_element
 %type <interface_list>    interface_list entity_header port_clause
 %type <port_mode>  mode
 
+%type <arch_statement> concurrent_statement concurrent_signal_assignment_statement
+%type <arch_statement_list> architecture_statement_part
+
 %%
 
  /* The design_file is the root for the VHDL parse. */
@@ -101,11 +108,12 @@ architecture_body
     K_of IDENTIFIER
     K_is
     K_begin architecture_statement_part K_end K_architecture_opt ';'
-      { Architecture*tmp = new Architecture(lex_strings.make($2));
+      { Architecture*tmp = new Architecture(lex_strings.make($2), *$7);
 	FILE_NAME(tmp, @1);
 	bind_architecture_to_entity($4, tmp);
 	delete[]$2;
 	delete[]$4;
+	delete $7;
       }
   | K_architecture IDENTIFIER
     K_of IDENTIFIER
@@ -120,11 +128,26 @@ architecture_body
      statements. */
 architecture_statement_part
   : architecture_statement_part concurrent_statement
+      { std::list<Architecture::Statement*>*tmp = $1;
+	tmp->push_back($2);
+	$$ = tmp;
+      }
   | concurrent_statement
+      { std::list<Architecture::Statement*>*tmp = new std::list<Architecture::Statement*>;
+	tmp->push_back($1);
+	$$ = tmp;
+      }
   ;
 
 concurrent_signal_assignment_statement
   : IDENTIFIER LEQ waveform ';'
+      { perm_string targ_name = lex_strings.make($1);
+	SignalAssignment*tmp = new SignalAssignment(targ_name);
+	FILE_NAME(tmp, @1);
+
+	$$ = tmp;
+	delete[]$1;
+      }
   ;
 
 concurrent_statement

vhdlpp/parse_wrap.h

@@ -28,6 +28,7 @@
 # include  <list>
 # include "vhdlint.h"
 # include "vhdlreal.h"
+# include  "architec.h"
 # include  "parse.h"
 
 #endif