Add regression tests for non-ANSI module port range mismatch

Check that when port direction and data type are declared separately that
an error is reported if the port direction has an explicit range
specification, but the data type has not. This should even be the case if
the data type has an implicit range, e.g `int` or a struct type.

For vector types also check that it is an error if the ranges are not
identical.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/module_nonansi_atom2_fail.v

@@ -0,0 +1,14 @@
+// Check that it is an error to declare a non-ANSI module port with implicit
+// packed dimensions if it is later redeclared as an atom2 typed variable. Even
+// if the size of the packed dimensions matches that of the size of the atom2
+// type.
+
+module test(x);
+  output [15:0] x;
+  shortint x;
+
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/module_nonansi_enum_fail.v

@@ -0,0 +1,17 @@
+// Check that it is an error to declare a non-ANSI module port with implicit
+// packed dimensions if it is later redeclared as a enum typed variable. Even if
+// the size of the packed dimensions matches that of the size of the enum type.
+
+typedef enum integer {
+  A, B
+} T;
+
+module test(x);
+  output [31:0] x;
+  T x;
+
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/module_nonansi_integer_fail.v

@@ -0,0 +1,14 @@
+// Check that it is an error to declare a non-ANSI module port with implicit
+// packed dimensions if it is later redeclared as an integer typed variable.
+// Even if the size of the packed dimensions matches that of the size of the
+// integer type.
+
+module test(x);
+  output [31:0] x;
+  integer x;
+
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/module_nonansi_parray_fail.v

@@ -0,0 +1,17 @@
+// Check that it is an error to declare a non-ANSI module port with implicit
+// packed dimensions if it is later redeclared as a packed array typed variable.
+// Even if the size of the packed dimensions matches that of the size of the
+// packed array.
+
+typedef reg [7:0] T1;
+typedef T1 [3:0] T2;
+
+module test(x);
+  output [31:0] x;
+  T2 x;
+
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/module_nonansi_real_fail.v

@@ -0,0 +1,12 @@
+// Check that it is an error to declare a non-ANSI module port with implicit
+// packed dimensions if it is later redeclared as a real typed variable.
+
+module test(x);
+  output [3:0] x;
+  real x;
+
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/module_nonansi_struct_fail.v

@@ -0,0 +1,19 @@
+// Check that it is an error to declare a non-ANSI module port with implicit
+// packed dimensions if it is later redeclared as a packed struct typed
+// variable. Even if the size of the packed dimensions matches that of the size
+// of the struct.
+
+typedef struct packed {
+  reg [31:0] x;
+  reg [7:0] y;
+} T;
+
+module test(x);
+  output [47:0] x;
+  T x;
+
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/module_nonansi_time_fail.v

@@ -0,0 +1,13 @@
+// Check that it is an error to declare a non-ANSI module port with implicit
+// packed dimensions if it is later redeclared as a time typed variable. Even if
+// the size of the packed dimensions matches that of the size of the time type.
+
+module test(x);
+  output [63:0] x;
+  time x;
+
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/module_nonansi_vec_fail1.v

@@ -0,0 +1,13 @@
+// Check that it is an error to declare a non-ANSI module port with implicit
+// packed dimensions if it is later redeclared as a vector typed variable and
+// the size of the packed dimensions do not match.
+
+module test(x);
+  output [3:0] x;
+  reg [7:0] x;
+
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/module_nonansi_vec_fail2.v

@@ -0,0 +1,13 @@
+// Check that it is an error to declare a non-ANSI module port without implicit
+// packed dimensions if it is later redeclared as a vector typed variable and
+// the vector type is not a scalar.
+
+module test(x);
+  output x;
+  reg [7:0] x;
+
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/module_nonansi_vec_fail3.v

@@ -0,0 +1,13 @@
+// Check that it is an error to declare a non-ANSI module port with implicit
+// packed dimensions if it is later redeclared as a vector typed variable and
+// the vector type is a scalar.
+
+module test(x);
+  output [7:0] x;
+  reg x;
+
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule

ivtest/regress-sv.list

@@ -351,16 +351,21 @@ localparam_type2	normal,-g2009		ivltests
 logical_short_circuit	normal,-g2012		ivltests
 logp2			normal,-g2005-sv	ivltests
 mod_inst_pkg		normal,-g2009		ivltests
+module_nonansi_atom2_fail CE,-g2005-sv	ivltests
 module_nonansi_enum1	normal,-g2005-sv	ivltests
 module_nonansi_enum2	normal,-g2005-sv	ivltests
+module_nonansi_enum_fail CE,-g2005-sv	ivltests
 module_nonansi_int1	normal,-g2005-sv	ivltests
 module_nonansi_int2	normal,-g2005-sv	ivltests
 module_nonansi_parray1	normal,-g2005-sv	ivltests
 module_nonansi_parray2	normal,-g2005-sv	ivltests
+module_nonansi_parray_fail CE,-g2005-sv	ivltests
 module_nonansi_real1	normal,-g2005-sv	ivltests
 module_nonansi_real2	normal,-g2005-sv	ivltests
+module_nonansi_real_fail CE,-g2005-sv	ivltests
 module_nonansi_struct1	normal,-g2005-sv	ivltests
 module_nonansi_struct2	normal,-g2005-sv	ivltests
+module_nonansi_struct_fail CE,-g2005-sv	ivltests
 module_output_port_sv_var1 normal,-g2005-sv	ivltests
 module_output_port_sv_var2 normal,-g2005-sv	ivltests
 named_begin		normal,-g2009		ivltests

ivtest/regress-vlg.list

@@ -656,10 +656,15 @@ module_input_port_list_def CE			ivltests # input ports only support default valu
 module_input_port_type	CE			ivltests
 module_nonansi_integer1	normal			ivltests
 module_nonansi_integer2	normal			ivltests
+module_nonansi_integer_fail CE			ivltests
 module_nonansi_time1	normal			ivltests
 module_nonansi_time2	normal			ivltests
+module_nonansi_time_fail CE			ivltests
 module_nonansi_vec1	normal			ivltests
 module_nonansi_vec2	normal			ivltests
+module_nonansi_vec_fail1 CE			ivltests
+module_nonansi_vec_fail2 CE			ivltests
+module_nonansi_vec_fail3 CE			ivltests
 module_output_port_list_def normal		ivltests
 module_output_port_var1	normal			ivltests
 module_output_port_var2	normal			ivltests