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Better job of matching adder operand sizes for vec4 code generator.

This commit is contained in:
Stephen Williams 2014-02-10 18:06:56 -08:00
parent e66fc7e5cc
commit 801e795112
2 changed files with 3 additions and 3 deletions
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4
tgt-vvp/eval_vec4.c
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@ -55,11 +55,11 @@ static void draw_binary_vec4_arith(ivl_expr_t expr, int stuff_ok_flag)
assume that the core has not given us an operand wider then
the expression width. So padd operands as needed. */
draw_eval_vec4(le, stuff_ok_flag);
if (lwid < ewid) {
if (lwid != ewid) {
fprintf(vvp_out, " %%pad/%c %u;\n", ivl_expr_signed(le)? 's' : 'u', ewid);
}
draw_eval_vec4(re, stuff_ok_flag);
if (rwid < ewid) {
if (rwid != ewid) {
fprintf(vvp_out, " %%pad/%c %u;\n", ivl_expr_signed(re)? 's' : 'u', ewid);
}

2
vvp/vthread.cc
View File

@ -936,7 +936,7 @@ bool of_ADD(vthread_t thr, vvp_code_t)
vvp_vector4_t l = thr->pop_vec4();
unsigned wid = l.size();
assert(wid = r.size());
assert(wid == r.size());
unsigned long*lva = l.subarray(0,wid);
unsigned long*lvb = r.subarray(0,wid);