Dummy code for handling function scopes

tgt-vhdl/scope.cc

@@ -366,6 +366,21 @@ static int draw_module(ivl_scope_t scope, ivl_scope_t parent)
    return 0;
 }
 
+/*
+ * Create a VHDL function from a Verilog function definition.
+ */
+int draw_function(ivl_scope_t scope, ivl_scope_t parent)
+{
+   assert(ivl_scope_type(scope) == IVL_SCT_FUNCTION);
+
+   // Find the containing entity
+   vhdl_entity *ent = find_entity(ivl_scope_tname(parent));
+   assert(ent);
+
+   return 1;
+}
+
+
 int draw_scope(ivl_scope_t scope, void *_parent)
 {
    ivl_scope_t parent = static_cast<ivl_scope_t>(_parent);
@@ -376,6 +391,9 @@ int draw_scope(ivl_scope_t scope, void *_parent)
    case IVL_SCT_MODULE:
       rc = draw_module(scope, parent);
       break;
+   case IVL_SCT_FUNCTION:
+      rc = draw_function(scope, parent);
+      break;
    default:
       error("No VHDL conversion for %s (at %s)",
             ivl_scope_tname(scope),

tgt-vhdl/vhdl_syntax.hh

@@ -543,6 +543,12 @@ private:
    bool init_;
 };
 
+
+/*
+ * Any sort of procedural element: process, function, or
+ * procedure. Roughly these map onto Verilog's processes,
+ * functions, and tasks.
+ */
 class vhdl_procedural {
 public:
    virtual ~vhdl_procedural() {}
@@ -554,6 +560,17 @@ protected:
    vhdl_scope scope_;
 };
 
+
+class vhdl_function : public vhdl_decl, public vhdl_procedural {
+public:
+   vhdl_function(const char *name, vhdl_type *ret_type)
+      : vhdl_decl(name, ret_type) {}
+
+   void emit(std::ofstream &of, int level) const;
+private:
+};
+
+
 class vhdl_process : public vhdl_conc_stmt, public vhdl_procedural {
 public:
    vhdl_process(const char *name = "") : name_(name) {}