Fix space issues in a couple files

README.txt

@@ -77,12 +77,12 @@ the configure scripts.
 Unpack the tar-ball and cd into the verilog-######### directory
 (presumably that is how you got to this README) and compile the source
 with the commands:
-	
+
   ./configure
   make
 
 If you are building from git, you have to run the command below before
-compile the source. This will generate the "configure" file, which is 
+compile the source. This will generate the "configure" file, which is
 automatically done when building from tarball.
 
   sh autoconf.sh

tgt-vhdl/stmt.cc

@@ -1250,7 +1250,7 @@ static void process_number(vhdl_binop_expr *all, vhdl_var_ref *test,
       switch (bits[i]) {
       case 'x':
          if (is_casez) break;
-         // fallthrough 
+         // fallthrough
       case '?':
       case 'z':
          continue;  // Ignore these.