Allow to declare direction after data type for non-ANSI ports

When using non-ANSI ports (System)Verilog allows to have separate
declarations for the port direction and data type. E.g.

```
input x;
reg x;
```

It is also allowed to first declare the data type and then the port type.
E.g.

```
reg x;
input x;
```

Currently this fails with an error message. Add support for handling this
by allowing to change the port type of a signal from `NOT_A_PORT` to port
direction.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

PWire.cc

@@ -98,12 +98,10 @@ bool PWire::set_port_type(NetNet::PortType pt)
 
       switch (port_type_) {
 	  case NetNet::PIMPLICIT:
+	  case NetNet::NOT_A_PORT:
 	    port_type_ = pt;
 	    return true;
 
-	  case NetNet::NOT_A_PORT:
-	    return false;
-
 	  default:
 	    if (port_type_ != pt)
 		  return false;

pform.cc

@@ -3413,18 +3413,12 @@ static void pform_set_port_type(const struct vlltype&li,
       }
 
       switch (cur->get_port_type()) {
+	  case NetNet::NOT_A_PORT:
 	  case NetNet::PIMPLICIT:
 	    if (! cur->set_port_type(pt))
 		  VLerror("error setting port direction.");
 	    break;
 
-	  case NetNet::NOT_A_PORT:
-	    cerr << li << ": error: "
-		 << "port " << name << " is not in the port list."
-		 << endl;
-	    error_count += 1;
-	    break;
-
 	  default:
 	    cerr << li << ": error: "
 		 << "port " << name << " already has a port declaration."