Fix implicit casts in assignments (part 3).
This patch adds support for bool/bit vector types on the LHS of a parameter declaration and ensures implicit casts in parameter declarations are performed where necessary.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2000-2012 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2000-2013 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -452,7 +452,8 @@ void NetScope::evaluate_parameter_logic_(Design*des, param_ref_t cur)
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lv_width = (msb >= lsb) ? 1 + msb - lsb : 1 + lsb - msb;
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NetExpr*expr = elab_and_eval(des, val_scope, val_expr, lv_width, true,
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(*cur).second.is_annotatable);
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(*cur).second.is_annotatable,
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(*cur).second.type);
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if (! expr)
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return;
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@ -491,15 +492,7 @@ void NetScope::evaluate_parameter_logic_(Design*des, param_ref_t cur)
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sure the type is set right. Note that if the parameter
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doesn't have an explicit type or range, then it will get
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the signedness from the expression itself. */
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if (range_flag) {
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/* If we have a real value convert it to an integer. */
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if(NetECReal*tmp = dynamic_cast<NetECReal*>(expr)) {
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verinum nval(tmp->value().as_long64(), (unsigned)lv_width);
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expr = new NetEConst(nval);
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expr->set_line(*((*cur).second.val));
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(*cur).second.val = expr;
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}
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if ((*cur).second.type != IVL_VT_NO_TYPE) {
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(*cur).second.val->cast_signed((*cur).second.signed_flag);
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} else if ((*cur).second.signed_flag) {
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(*cur).second.val->cast_signed(true);
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@ -574,7 +567,8 @@ void NetScope::evaluate_parameter_real_(Design*des, param_ref_t cur)
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NetScope*val_scope = (*cur).second.val_scope;
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NetExpr*expr = elab_and_eval(des, val_scope, val_expr, -1, true,
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(*cur).second.is_annotatable);
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(*cur).second.is_annotatable,
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(*cur).second.type);
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if (! expr)
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return;
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@ -594,26 +588,10 @@ void NetScope::evaluate_parameter_real_(Design*des, param_ref_t cur)
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}
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break;
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case IVL_VT_LOGIC:
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case IVL_VT_BOOL:
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if (NetEConst*tmp = dynamic_cast<NetEConst*>(expr)) {
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verireal val (tmp->value().as_long());
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res = new NetECReal(val);
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res->set_line(*tmp);
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} else {
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cerr << expr->get_fileline()
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<< ": error: "
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<< "Unable to evaluate parameter "
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<< (*cur).first << " value: " << *expr << endl;
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des->errors += 1;
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return;
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}
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break;
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default:
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cerr << expr->get_fileline()
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<< ": internal error: "
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<< "Unhandled expression type?" << endl;
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<< "Failed to cast expression?" << endl;
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des->errors += 1;
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return;
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break;
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@ -683,6 +661,7 @@ void NetScope::evaluate_parameter_(Design*des, param_ref_t cur)
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} else {
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cur->second.solving = true;
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switch (cur->second.type) {
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case IVL_VT_NO_TYPE:
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case IVL_VT_BOOL:
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case IVL_VT_LOGIC:
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evaluate_parameter_logic_(des, cur);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2000-2012 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2000-2013 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -138,8 +138,6 @@ void NetScope::set_parameter(perm_string key, bool is_annotatable,
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ref.range = range_list;
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ref.val = 0;
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ref.set_line(file_line);
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ivl_assert(file_line, type__ != IVL_VT_NO_TYPE);
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}
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/*
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34
parse.y
34
parse.y
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@ -573,7 +573,7 @@ static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>
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%type <nettype> net_type var_type net_type_opt
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%type <gatetype> gatetype switchtype
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%type <porttype> port_direction port_direction_opt
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%type <vartype> bit_logic
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%type <vartype> bit_logic bit_logic_opt
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%type <vartype> integer_vector_type
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%type <parmvalue> parameter_value_opt
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@ -4449,9 +4449,15 @@ net_decl_assigns
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bit_logic
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: K_logic { $$ = IVL_VT_LOGIC; }
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| K_bool { $$ = IVL_VT_BOOL; /* Icarus misc */}
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| K_bit { $$ = IVL_VT_BOOL; /* IEEE1800 / IEEE1364-2009 */}
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;
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bit_logic_opt
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: bit_logic
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| { $$ = IVL_VT_NO_TYPE; }
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;
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net_type
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: K_wire { $$ = NetNet::WIRE; }
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| K_tri { $$ = NetNet::TRI; }
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@ -4476,25 +4482,13 @@ var_type
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;
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param_type
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:
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{ param_active_range = 0;
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param_active_signed = false;
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param_active_type = IVL_VT_LOGIC;
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}
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| range
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{ param_active_range = $1;
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param_active_signed = false;
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param_active_type = IVL_VT_LOGIC;
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}
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| K_signed
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{ param_active_range = 0;
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param_active_signed = true;
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param_active_type = IVL_VT_LOGIC;
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}
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| K_signed range
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{ param_active_range = $2;
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param_active_signed = true;
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param_active_type = IVL_VT_LOGIC;
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: bit_logic_opt unsigned_signed_opt range_opt
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{ param_active_range = $3;
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param_active_signed = $2;
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if (($1 == IVL_VT_NO_TYPE) && ($3 != 0))
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param_active_type = IVL_VT_LOGIC;
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else
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param_active_type = $1;
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}
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| K_integer
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{ param_active_range = make_range_from_width(integer_width);
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