Add regression tests for net declaration assignments

Check that SystemVerilog net declarations can mix entries with and
without initialization.

Check that in SystemVerilog it is possible to do assignments within net array
declarations.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/sv_net_array_decl_assign.v

@@ -0,0 +1,27 @@
+// Check that net arrays can be initialized during declaration.
+
+module test;
+
+  reg failed;
+
+  wire [3:0] a[0:1] = '{4'h1, 4'h2};
+
+  `define check(val, exp) \
+    if (val !== exp) begin \
+      $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, \
+               `"val`", exp, val); \
+      failed = 1'b1; \
+    end
+
+  initial begin
+    failed = 1'b0;
+
+    `check(a[0], 4'h1)
+    `check(a[1], 4'h2)
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+
+endmodule

ivtest/ivltests/sv_net_decl_assign.v

@@ -0,0 +1,33 @@
+// Check that net declarations can mix initialized and uninitialized entries.
+
+module test;
+
+  reg failed;
+
+  wire [3:0] a, b = 4'h5;
+  wire [3:0] c = 4'ha, d;
+
+  assign a = b;
+  assign d = c;
+
+  `define check(val, exp) \
+    if (val !== exp) begin \
+      $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, \
+               `"val`", exp, val); \
+      failed = 1'b1; \
+    end
+
+  initial begin
+    failed = 1'b0;
+
+    `check(a, 4'h5)
+    `check(b, 4'h5)
+    `check(c, 4'ha)
+    `check(d, 4'ha)
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+
+endmodule

ivtest/regress-vvp.list

@@ -342,6 +342,8 @@ sv_module_port1			vvp_tests/sv_module_port1.json
 sv_module_port2			vvp_tests/sv_module_port2.json
 sv_module_port3			vvp_tests/sv_module_port3.json
 sv_module_port4			vvp_tests/sv_module_port4.json
+sv_net_array_decl_assign	vvp_tests/sv_net_array_decl_assign.json
+sv_net_decl_assign		vvp_tests/sv_net_decl_assign.json
 sv_package_lifetime		vvp_tests/sv_package_lifetime.json
 sv_package_lifetime_fail	vvp_tests/sv_package_lifetime_fail.json
 sv_parameter_type		vvp_tests/sv_parameter_type.json

ivtest/vvp_tests/sv_net_array_decl_assign.json

@@ -0,0 +1,9 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_net_array_decl_assign.v",
+    "iverilog-args" : [ "-g2005-sv" ],
+    "vlog95" : {
+        "__comment" : "Array nets are not supported",
+        "type"      : "CE"
+    }
+}

ivtest/vvp_tests/sv_net_decl_assign.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_net_decl_assign.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}