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Merge branch 'master' of steve-icarus@icarus.com:git/verilog

This commit is contained in:
Stephen Williams 2007-09-04 16:42:45 -07:00
parent 083b9b6ee6 b55e3c11dc
commit 203cb0f730
2 changed files with 17 additions and 0 deletions
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12
elaborate.cc
View File

@ -379,6 +379,12 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
only. We do it early so that we can see if we can make a
wide gate instead of an array of gates. */
if (pin(0) == 0) {
cerr << get_line() << ": error: Logic gate port "
"expressions are not optional." << endl;
des->errors += 1;
return;
}
NetNet*lval_sig = pin(0)->elaborate_lnet(des, scope, true);
assert(lval_sig);
@ -536,6 +542,12 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) {
const PExpr*ex = pin(idx);
if (ex == 0) {
cerr << get_line() << ": error: Logic gate port "
"expressions are not optional." << endl;
des->errors += 1;
return;
}
NetNet*sig = (idx == 0)
? lval_sig
: ex->elaborate_net(des, scope, 0, 0, 0, 0);

5
vpi/lxt_write.h
View File

@ -32,6 +32,11 @@
#include <zlib.h>
#include <bzlib.h>
#if defined _MSC_VER || defined __MINGW32__
#define fseeko fseek
#define ftello ftell
#endif
typedef struct dslxt_tree_node dslxt_Tree;
struct dslxt_tree_node {