More test version cleanup
This commit is contained in:
Cary R
parent
57524836f1
commit
91b1759602
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@ -51,9 +51,7 @@ or if perl is located in /usr/bin
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./vpi_reg.pl
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All these tests should pass for V11.devel. There are
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some expected failures for V10, which are flagged as
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Not Implemented
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All these tests should pass.
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The individual test results are found in the vpi_log
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directory and the gold files are in the vpi_gold
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@ -81,9 +79,7 @@ or if perl is located in /usr/bin
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./vhdl_reg.pl
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The expected output for V0.10.devel and V0.9 is located
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in the vhdl_regression_report-devel.txt file. V0.8 does
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not support converting Verilog to VHDL.
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The tests are expected to pass except for the tri* tests.
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This script also takes the --suffix=<suffix> and the
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--with-valgrind flags described above.
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@ -4,7 +4,7 @@
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#
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# This script is based on code with the following Copyright.
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#
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# Copyright (c) 1999-2020 Guy Hutchison (ghutchis@pacbell.net)
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# Copyright (c) 1999-2023 Guy Hutchison (ghutchis@pacbell.net)
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#
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# This source code is free software; you can redistribute it
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# and/or modify it in source code form under the terms of the GNU
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@ -49,19 +49,11 @@ if ($#ARGV != -1) {
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&read_regression_list("regress-fsv.list", $ver, $force_sv, "");
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}
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&read_regression_list("regress-vlog95.list", $ver, $force_sv, "");
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&read_regression_list("regress-v$ver.list", $ver, $force_sv, "");
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&read_regression_list("regress-ivl1.list", $ver, $force_sv, "");
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&read_regression_list("regress-vlg.list", $ver, $force_sv, "");
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&read_regression_list("regress-vams.list", $ver, $force_sv, "");
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if ($ver >= 10) {
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&read_regression_list("regress-sv.list", $ver, $force_sv, "");
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&read_regression_list("regress-vhdl.list", $ver, $force_sv, "");
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}
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if ($ver == 0.9) {
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&read_regression_list("regress-synth.list", $ver, $force_sv, "");
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} else {
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&read_regression_list("regress-synth.list", $ver, $force_sv, "-S");
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}
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&read_regression_list("regress-ivl1.list", $ver, $force_sv, "");
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&read_regression_list("regress-vlg.list", $ver, $force_sv, "");
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&read_regression_list("regress-sv.list", $ver, $force_sv, "");
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&read_regression_list("regress-vhdl.list", $ver, $force_sv, "");
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&read_regression_list("regress-synth.list", $ver, $force_sv, "-S");
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}
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&execute_regression($suffix, $with_valg);
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&close_report_file;
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@ -80,11 +80,7 @@ static PLI_INT32 dump_specify_calltf(PLI_BYTE8*name)
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delays.time_type = vpiSimTime;
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delays.mtm_flag = 0;
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delays.append_flag = 0;
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#ifdef IVERILOG_V10
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delays.plusere_flag = 0;
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#else
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delays.pulsere_flag = 0;
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#endif
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vpi_get_delays(item, &delays);
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vpi_printf("** (%d,%d,%d, %d,%d,%d, %d,%d,%d, %d,%d,%d)\n",
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(int)delay_times[0].low,
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@ -105,11 +101,7 @@ static PLI_INT32 dump_specify_calltf(PLI_BYTE8*name)
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delays.time_type = vpiScaledRealTime;
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delays.mtm_flag = 0;
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delays.append_flag = 0;
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#ifdef IVERILOG_V10
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delays.plusere_flag = 0;
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#else
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delays.pulsere_flag = 0;
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#endif
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vpi_get_delays(item, &delays);
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vpi_printf("** (%f,%f,%f, %f,%f,%f, %f,%f,%f, %f,%f,%f)\n",
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delay_times[0].real,
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@ -145,11 +137,7 @@ static PLI_INT32 dump_specify_calltf(PLI_BYTE8*name)
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delays.time_type = vpiScaledRealTime;
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delays.mtm_flag = 0;
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delays.append_flag = 0;
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#ifdef IVERILOG_V10
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delays.plusere_flag = 0;
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#else
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delays.pulsere_flag = 0;
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#endif
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vpi_get_delays(item, &delays);
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vpi_printf("** (%f,%f,%f, %f,%f,%f, %f,%f,%f, %f,%f,%f)\n",
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delay_times[0].real,
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@ -1,41 +0,0 @@
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Compiling vpi/pr723.c...
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Making pr723.vpi from pr723.o...
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Open some files
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open MCD returned 00000002
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open MCD returned 00000004
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open MCD returned 00000008
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open MCD returned 00000010
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open FD ('r') returned 80000003
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open FD ('r') returned 80000004
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open FD ('w') returned 80000005
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open FD ('w') returned 80000006
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open FD ('a') returned 80000007
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open FD ('a') returned 80000008
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MCD 01: stdout
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MCD 02: /dev/null
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MCD 03: /dev/null
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MCD 04: /dev/null
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MCD 05: /dev/null
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FP 00: stdin
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FP 01: stdout
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FP 02: stderr
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FP 03: /dev/null
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FP 04: /dev/null
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FP 05: /dev/null
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FP 06: /dev/null
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FP 07: /dev/null
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FP 08: /dev/null
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write to MCD 1
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write to FD 2
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write to FD 1
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Close some files
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WARNING: vpi/pr723.v:48: invalid file descriptor/MCD (0x2) given to $fclose.
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WARNING: vpi/pr723.v:49: invalid file descriptor/MCD (0x40000000) given to $fclose.
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WARNING: vpi/pr723.v:54: invalid file descriptor/MCD (0x80000003) given to $fclose.
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WARNING: vpi/pr723.v:57: invalid file descriptor/MCD (0x81ca1ca0) given to $fclose.
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MCD 01: stdout
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FP 00: stdin
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FP 01: stdout
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FP 02: stderr
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WARNING: vpi/pr723.v:63: invalid file descriptor/MCD (0x40000000) given to $fdisplay.
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WARNING: vpi/pr723.v:64: invalid file descriptor/MCD (0x8000000f) given to $fdisplay.
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@ -195,13 +195,8 @@ sub execute_regression {
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}
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$cmd = $with_valg ? "valgrind --trace-children=yes " : "";
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if ($ver < 11) {
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$cmd .= "iverilog$sfx $args{$tname} -o vsim vpi/$tname.v >> " .
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"vpi_log/$tname.log 2>&1";
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} else {
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$cmd .= "iverilog$sfx $args{$tname} -L . -m $tname -o vsim vpi/$tname.v >> " .
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"vpi_log/$tname.log 2>&1";
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}
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$cmd .= "iverilog$sfx $args{$tname} -L . -m $tname -o vsim vpi/$tname.v >> " .
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"vpi_log/$tname.log 2>&1";
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if (system("$cmd")) {
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print "==> Failed - running iverilog.\n";
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$failed++;
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@ -210,11 +205,7 @@ sub execute_regression {
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$cmd = $with_valg ? "valgrind --leak-check=full " .
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"--show-reachable=yes " : "";
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if ($ver < 11) {
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$cmd .= "vvp$sfx -M . -m $tname vsim >> vpi_log/$tname.log 2>&1";
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} else {
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$cmd .= "vvp$sfx vsim >> vpi_log/$tname.log 2>&1";
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}
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$cmd .= "vvp$sfx vsim >> vpi_log/$tname.log 2>&1";
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if (system("$cmd")) {
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print "==> Failed - running vvp.\n";
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$failed++;
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@ -54,23 +54,6 @@ vstd:scopes normal scopes.c scopes-std.log
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msys2:pr723 NI pr723.c pr723.log
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#==========
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# V10 exceptions
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#==========
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# V10 exceptions
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v10:br_gh117 NI br_gh117.c br_gh117.gold
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v10:br_ml20191013 NI br_ml20191013.c br_ml20191013.gold
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v10:by_index NI by_index.c by_index.gold
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v10:pr723 normal pr723.c pr723-v10.log
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v10:spec_delays normal,-gspecify spec_delays.c spec_delays.log -DIVERILOG_V10
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#==========
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# V11 exceptions
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#==========
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#==========
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# The default case.
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#==========
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@ -4,7 +4,7 @@
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#
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# This script is based on code with the following Copyright.
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#
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# Copyright (c) 1999-2021 Guy Hutchison (ghutchis@pacbell.net)
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# Copyright (c) 1999-2023 Guy Hutchison (ghutchis@pacbell.net)
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#
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# This source code is free software; you can redistribute it
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# and/or modify it in source code form under the terms of the GNU
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@ -53,11 +53,9 @@ if ($#ARGV != -1) {
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}
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&read_regression_list("regress-ivl1.list", $ver, $force_sv, "");
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&read_regression_list("regress-vlg.list", $ver, $force_sv, "");
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if ($ver >= 10) {
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&read_regression_list("regress-sv.list", $ver, $force_sv, "");
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&read_regression_list("regress-vhdl.list", $ver, $force_sv, "");
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}
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if ($ver == 0.9 or $force_sv) {
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&read_regression_list("regress-sv.list", $ver, $force_sv, "");
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&read_regression_list("regress-vhdl.list", $ver, $force_sv, "");
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if ($force_sv) {
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&read_regression_list("regress-synth.list", $ver, $force_sv, "");
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} else {
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&read_regression_list("regress-synth.list", $ver, $force_sv, "-S");
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