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Merge branch 'master' of steve-icarus@icarus.com:git/verilog

This commit is contained in:
Stephen Williams 2008-03-02 21:04:46 -08:00
parent 32a2e7aa39 f8caebd076
commit cb920bd864
5 changed files with 68 additions and 29 deletions
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26
dup_expr.cc
View File

@ -24,14 +24,17 @@
NetEBComp* NetEBComp::dup_expr() const
{
NetEBComp*result = new NetEBComp(op_, left_->dup_expr(),
right_->dup_expr());
return result;
NetEBComp*tmp = new NetEBComp(op_, left_->dup_expr(),
right_->dup_expr());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
NetEConst* NetEConst::dup_expr() const
{
NetEConst*tmp = new NetEConst(value_);
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@ -39,6 +42,7 @@ NetEConst* NetEConst::dup_expr() const
NetEConstParam* NetEConstParam::dup_expr() const
{
NetEConstParam*tmp = new NetEConstParam(scope_, name_, value());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@ -46,6 +50,7 @@ NetEConstParam* NetEConstParam::dup_expr() const
NetECRealParam* NetECRealParam::dup_expr() const
{
NetECRealParam*tmp = new NetECRealParam(scope_, name_, value());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@ -64,9 +69,12 @@ NetEScope* NetEScope::dup_expr() const
NetESelect* NetESelect::dup_expr() const
{
return new NetESelect(expr_->dup_expr(),
base_? base_->dup_expr() : 0,
expr_width());
NetESelect*tmp = new NetESelect(expr_->dup_expr(),
base_? base_->dup_expr() : 0,
expr_width());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
NetESFunc* NetESFunc::dup_expr() const
@ -80,6 +88,7 @@ NetESFunc* NetESFunc::dup_expr() const
tmp->parm(idx, tmp->parm(idx)->dup_expr());
}
tmp->set_line(*this);
return tmp;
}
@ -96,6 +105,8 @@ NetETernary* NetETernary::dup_expr() const
NetETernary*tmp = new NetETernary(cond_->dup_expr(),
true_val_->dup_expr(),
false_val_->dup_expr());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@ -112,6 +123,7 @@ NetEUFunc* NetEUFunc::dup_expr() const
tmp = new NetEUFunc(scope_, func_, result_sig_->dup_expr(), tmp_parms);
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@ -119,6 +131,7 @@ NetEUnary* NetEUnary::dup_expr() const
{
NetEUnary*tmp = new NetEUnary(op_, expr_->dup_expr());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@ -126,5 +139,6 @@ NetEUReduce* NetEUReduce::dup_expr() const
{
NetEUReduce*tmp = new NetEUReduce(op_, expr_->dup_expr());
assert(tmp);
tmp->set_line(*this);
return tmp;
}

9
elab_pexpr.cc
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2007 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@ -187,6 +187,7 @@ NetExpr*PEIdent::elaborate_pexpr(Design*des, NetScope*scope) const
NetExpr*tmp = name_tail.index.back().msb->elaborate_pexpr(des, scope);
if (tmp != 0) {
res = new NetESelect(res, tmp, 1);
res->set_line(*this);
}
break;
}
@ -216,7 +217,10 @@ NetETernary* PETernary::elaborate_pexpr(Design*des, NetScope*scope) const
if (c == 0) return 0;
if (t == 0) return 0;
if (f == 0) return 0;
return new NetETernary(c, t, f);
NetETernary*tmp = new NetETernary(c, t, f);
tmp->set_line(*this);
return tmp;
}
NetExpr*PEUnary::elaborate_pexpr (Design*des, NetScope*scope) const
@ -251,4 +255,3 @@ NetExpr*PEUnary::elaborate_pexpr (Design*des, NetScope*scope) const
}
return tmp;
}

45
elab_sig.cc
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2007 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@ -35,6 +35,32 @@
# include "util.h"
# include "ivl_assert.h"
static bool get_const_argument(NetExpr*exp, verinum&res)
{
switch (exp->expr_type()) {
case IVL_VT_REAL: {
NetECReal*cv = dynamic_cast<NetECReal*>(exp);
if (cv == 0) return false;
verireal tmp = cv->value();
res = verinum(tmp.as_long());
break;
}
case IVL_VT_BOOL:
case IVL_VT_LOGIC: {
NetEConst*cv = dynamic_cast<NetEConst*>(exp);
if (cv == 0) return false;
res = cv->value();
break;
}
default:
assert(0);;
}
return true;
}
void Statement::elaborate_sig(Design*des, NetScope*scope) const
{
}
@ -741,10 +767,14 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
return 0;
}
NetEConst*lcon = dynamic_cast<NetEConst*> (lexp);
NetEConst*rcon = dynamic_cast<NetEConst*> (rexp);
bool const_flag = true;
verinum lval, rval;
const_flag &= get_const_argument(lexp, lval);
const_flag &= get_const_argument(rexp, rval);
delete rexp;
delete lexp;
if ((lcon == 0) || (rcon == 0)) {
if (!const_flag) {
cerr << get_fileline() << ": internal error: The indices "
<< "are not constant for array ``"
<< name_ << "''." << endl;
@ -752,12 +782,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
return 0;
}
verinum lval = lcon->value();
verinum rval = rcon->value();
delete lexp;
delete rexp;
array_dimensions = 1;
array_s0 = lval.as_long();
array_e0 = rval.as_long();
@ -833,4 +857,3 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
return sig;
}

9
vvp/opcodes.txt
View File

@ -342,9 +342,9 @@ bits 4/5/6 just line %ix/get.
This instruction loads an immediate value into the addressed index
register. The index register holds numeric values, so the <value> is a
number. The idx value selects the index register, and may be 0, 1, 2
or 3. This is different from %ix/get, which loads the index register
from a value in the thread bit vector.
number. The idx value selects the index register. This is different
from %ix/get, which loads the index register from a value in the
thread bit vector.
* %ix/add <idx>, <value>
@ -353,8 +353,7 @@ from a value in the thread bit vector.
This instruction adds, subtracts, or multiplies an immediate value to
the addressed index register. The index register holds numeric values,
so the <value> is a number. The <idx> value selects the index register,
and may be 0, 1, 2 or 3.
so the <value> is a number. The <idx> value selects the index register.
* %jmp <code-label>

8
vvp/vthread.cc
View File

@ -1840,25 +1840,25 @@ bool of_INV(vthread_t thr, vvp_code_t cp)
bool of_IX_ADD(vthread_t thr, vvp_code_t cp)
{
thr->words[cp->bit_idx[0] & 3].w_int += cp->number;
thr->words[cp->bit_idx[0]].w_int += cp->number;
return true;
}
bool of_IX_SUB(vthread_t thr, vvp_code_t cp)
{
thr->words[cp->bit_idx[0] & 3].w_int -= cp->number;
thr->words[cp->bit_idx[0]].w_int -= cp->number;
return true;
}
bool of_IX_MUL(vthread_t thr, vvp_code_t cp)
{
thr->words[cp->bit_idx[0] & 3].w_int *= cp->number;
thr->words[cp->bit_idx[0]].w_int *= cp->number;
return true;
}
bool of_IX_LOAD(vthread_t thr, vvp_code_t cp)
{
thr->words[cp->bit_idx[0] & 3].w_int = cp->number;
thr->words[cp->bit_idx[0]].w_int = cp->number;
return true;
}