Rework VHDL assignment statement generation
This changes the assignment statement generator so that each VHDL declaration "knows" which type of assignment statement can/should be used on (i.e. signals must be assigned with <=). This will help us catch cases when we try to use, for example, := with signals. This occurs in pr2362211 where we try to assign to a signal within a function (where only := can be used).
This commit is contained in:
Nick Gasson
Stephen Williams
parent
c06c49c992
commit
d689c93879
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@ -162,10 +162,26 @@ static bool assignment_lvals(ivl_statement_t stmt, vhdl_procedural *proc,
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return true;
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}
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/*
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* Generate the right sort of assignment statement for assigning
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* `lhs' to `rhs'.
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*/
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static vhdl_abstract_assign_stmt *
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assign_for(vhdl_decl::assign_type_t atype, vhdl_var_ref *lhs, vhdl_expr *rhs)
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{
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switch (atype) {
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case vhdl_decl::ASSIGN_BLOCK:
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return new vhdl_assign_stmt(lhs, rhs);
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case vhdl_decl::ASSIGN_NONBLOCK:
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return new vhdl_nbassign_stmt(lhs, rhs);
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default:
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assert(false);
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}
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}
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/*
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* Generate an assignment of type T for the Verilog statement stmt.
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*/
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template <class T>
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void make_assignment(vhdl_procedural *proc, stmt_container *container,
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ivl_statement_t stmt, bool blocking)
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{
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@ -192,6 +208,11 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container,
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vhdl_expr *after = NULL;
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if ((i_delay = ivl_stmt_delay_expr(stmt)) != NULL)
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after = translate_time_expr(i_delay);
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// Find the declaration of the LHS so we know what type
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// of assignment statement to generate (is it a signal,
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// a variable, etc?)
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vhdl_decl *decl = proc->get_scope()->get_decl(lhs->get_name());
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// A small optimisation is to expand ternary RHSs into an
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// if statement (eliminates a function call and produces
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@ -209,7 +230,8 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container,
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// True part
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{
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T *a = new T(lhs, rhs);
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vhdl_abstract_assign_stmt *a =
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assign_for(decl->assignment_type(), lhs, rhs);
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if (after)
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a->set_after(after);
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vhdif->get_then_container()->add_stmt(a);
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@ -217,7 +239,8 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container,
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// False part
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{
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T *a = new T(lhs2, rhs2);
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vhdl_abstract_assign_stmt *a =
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assign_for(decl->assignment_type(), lhs2, rhs2);
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if (after)
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a->set_after(translate_time_expr(i_delay));
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vhdif->get_else_container()->add_stmt(a);
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@ -242,7 +265,6 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container,
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// The second test ensures that we only try to initialise
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// internal signals not ports
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ivl_lval_t lval = ivl_stmt_lval(stmt, 0);
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vhdl_decl *decl = proc->get_scope()->get_decl(lhs->get_name());
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if (proc->get_scope()->initializing()
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&& ivl_signal_port(ivl_lval_sig(lval)) == IVL_SIP_NONE
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&& !decl->has_initial()
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@ -260,8 +282,9 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container,
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return;
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}
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}
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T *a = new T(lhs, rhs);
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vhdl_abstract_assign_stmt *a =
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assign_for(decl->assignment_type(), lhs, rhs);
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container->add_stmt(a);
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if (after != NULL)
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@ -276,7 +299,7 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container,
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ostringstream ss;
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ss << "Verilog_Assign_Tmp_" << tmp_count++;
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string tmpname = ss.str();
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proc->get_scope()->add_decl
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(new vhdl_var_decl(tmpname.c_str(), new vhdl_type(*rhs->get_type())));
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@ -299,7 +322,13 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container,
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if ((i_delay = ivl_stmt_delay_expr(stmt)) != NULL)
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after = translate_time_expr(i_delay);
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T *a = new T(*it, tmp_rhs);
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// Find the declaration of the LHS so we know what type
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// of assignment statement to generate (is it a signal,
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// a variable, etc?)
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vhdl_decl *decl = proc->get_scope()->get_decl((*it)->get_name());
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vhdl_abstract_assign_stmt *a =
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assign_for(decl->assignment_type(), *it, tmp_rhs);
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if (after)
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a->set_after(after);
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@ -320,7 +349,7 @@ static int draw_nbassign(vhdl_procedural *proc, stmt_container *container,
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{
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assert(proc->get_scope()->allow_signal_assignment());
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make_assignment<vhdl_nbassign_stmt>(proc, container, stmt, false);
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make_assignment(proc, container, stmt, false);
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return 0;
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}
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@ -333,7 +362,7 @@ static int draw_assign(vhdl_procedural *proc, stmt_container *container,
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// followed by a zero-time wait
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// This follows the Verilog semantics fairly closely.
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make_assignment<vhdl_nbassign_stmt>(proc, container, stmt, false);
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make_assignment(proc, container, stmt, false);
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// Don't generate a zero-wait if this is the last statement in
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// the process
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@ -342,7 +371,7 @@ static int draw_assign(vhdl_procedural *proc, stmt_container *container,
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(new vhdl_wait_stmt(VHDL_WAIT_FOR, new vhdl_const_time(0)));
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}
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else
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make_assignment<vhdl_assign_stmt>(proc, container, stmt, true);
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make_assignment(proc, container, stmt, true);
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return 0;
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}
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@ -22,6 +22,7 @@
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#define INC_VHDL_SYNTAX_HH
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#include <inttypes.h>
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#include <cassert>
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#include "vhdl_element.hh"
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#include "vhdl_type.hh"
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@ -542,6 +543,16 @@ public:
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void set_type(vhdl_type *t) { type_ = t; }
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void set_initial(vhdl_expr *initial);
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bool has_initial() const { return has_initial_; }
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// The different sorts of assignment statement
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enum assign_type_t { ASSIGN_BLOCK, ASSIGN_NONBLOCK };
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// Get the sort of assignment statement to generate for
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// assignemnts to this declaration
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// For some sorts of declarations it doesn't make sense
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// to assign to it so calling assignment_type just raises
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// an assertion failure
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virtual assign_type_t assignment_type() const { assert(false); }
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protected:
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std::string name_;
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vhdl_type *type_;
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@ -577,7 +588,6 @@ public:
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void emit(std::ostream &of, int level) const;
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};
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/*
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* A variable declaration inside a process (although this isn't
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* enforced here).
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@ -587,6 +597,7 @@ public:
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vhdl_var_decl(const char *name, vhdl_type *type)
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: vhdl_decl(name, type) {}
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void emit(std::ostream &of, int level) const;
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assign_type_t assignment_type() const { return ASSIGN_BLOCK; }
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};
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@ -598,6 +609,7 @@ public:
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vhdl_signal_decl(const char *name, vhdl_type *type)
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: vhdl_decl(name, type) {}
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virtual void emit(std::ostream &of, int level) const;
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assign_type_t assignment_type() const { return ASSIGN_NONBLOCK; }
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};
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@ -632,6 +644,7 @@ public:
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void emit(std::ostream &of, int level) const;
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vhdl_port_mode_t get_mode() const { return mode_; }
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void set_mode(vhdl_port_mode_t m) { mode_ = m; }
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assign_type_t assignment_type() const { return ASSIGN_NONBLOCK; }
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private:
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vhdl_port_mode_t mode_;
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};
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