Add regression tests for issue #1258.

ivtest/gold/br_gh1258b-iverilog-stderr.gold

@@ -0,0 +1 @@
+ivltests/br_gh1258.v:7: warning: Timing checks are not supported.

ivtest/ivltests/br_gh1258.v

@@ -0,0 +1,12 @@
+module DFF (output reg Q, input CLK, D);
+        parameter [0:0] INIT = 1'b0;
+        initial Q = INIT;
+
+        specify
+                (posedge CLK => (Q : D)) = (480, 660);
+                $setup(D, posedge CLK, 576);
+        endspecify
+                
+        always @(posedge CLK)
+                Q <= D;
+endmodule

ivtest/regress-vvp.list

@@ -67,6 +67,8 @@ br_gh1184			vvp_tests/br_gh1184.json
 br_gh1242			vvp_tests/br_gh1242.json
 br_gh1256a			vvp_tests/br_gh1256a.json
 br_gh1256b			vvp_tests/br_gh1256b.json
+br_gh1258a			vvp_tests/br_gh1258a.json
+br_gh1258b			vvp_tests/br_gh1258b.json
 ca_time_real			vvp_tests/ca_time_real.json
 case1				vvp_tests/case1.json
 case2				vvp_tests/case2.json

ivtest/vvp_tests/br_gh1258a.json

@@ -0,0 +1,6 @@
+{
+    "type"   : "normal",
+    "source" : "br_gh1258.v",
+    "iverilog-args" : [ "-gno-specify" ],
+    "gold" : "br_gh1258a"
+}

ivtest/vvp_tests/br_gh1258b.json

@@ -0,0 +1,6 @@
+{
+    "type"   : "normal",
+    "source" : "br_gh1258.v",
+    "iverilog-args" : [ "-gspecify" ],
+    "gold" : "br_gh1258b"
+}