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Better handle some vector size matters for %load/v 

The %load/v instruction was doing some spurious resizes of the vector
that comes from the signal. Eliminate those resizes that can be
removed, and optimize some that remain.
This commit is contained in:
Stephen Williams 2008-06-11 14:38:35 -07:00
parent 608bad26cf
commit d7814ed767
2 changed files with 14 additions and 5 deletions
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12
vvp/vthread.cc
View File

@ -2461,7 +2461,6 @@ static vvp_vector4_t load_base(vthread_t thr, vvp_code_t cp)
assert(cp->bit_idx[0] >= 4);
assert(cp->bit_idx[1] > 0);
unsigned wid = cp->bit_idx[1];
vvp_net_t*net = cp->net;
/* For the %load to work, the functor must actually be a
@ -2473,10 +2472,7 @@ static vvp_vector4_t load_base(vthread_t thr, vvp_code_t cp)
assert(sig);
}
vvp_vector4_t sig_value = sig->vec4_value();
sig_value.resize(wid);
return sig_value;
return sig->vec4_value();
}
bool of_LOAD_VEC(vthread_t thr, vvp_code_t cp)
@ -2489,10 +2485,16 @@ bool of_LOAD_VEC(vthread_t thr, vvp_code_t cp)
/* Check the address once, before we scan the vector. */
thr_check_addr(thr, bit+wid-1);
if (sig_value.size() > wid)
sig_value.resize(wid);
/* Copy the vector bits into the bits4 vector. Do the copy
directly to skip the excess calls to thr_check_addr. */
thr->bits4.set_vec(bit, sig_value);
for (unsigned idx = sig_value.size() ; idx < wid ; idx += 1)
thr->bits4.set_bit(bit+idx, BIT4_X);
return true;
}

7
vvp/vvp_net.cc
View File

@ -404,6 +404,13 @@ void vvp_vector4_t::resize(unsigned newsize)
if (newsize > BITS_PER_WORD) {
unsigned newcnt = (newsize + BITS_PER_WORD - 1) / BITS_PER_WORD;
if (newcnt == cnt) {
// If the word count doesn't change, then there is
// no need for re-allocation so we are done now.
size_ = newsize;
return;
}
unsigned long*newbits = new unsigned long[2*newcnt];
if (cnt > 1) {