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Fix comparisons that use sb_to_idx()
A recent change to sb_to_idx() made it return a signed value where it previously returned an unsigned value. This patch adds explicit casts to remove the two signed vs unsigned comparison warning messages.
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+3
-2
@@ -1449,7 +1449,7 @@ NetExpr* PEIdent::elaborate_expr_net_part_(Design*des, NetScope*scope,
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}
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if (net->sig()->sb_to_idx(msv) >= net->vector_width()) {
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if (net->sig()->sb_to_idx(msv) >= (signed) net->vector_width()) {
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cerr << get_fileline() << ": error: part select ["
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<< msv << ":" << lsv << "] out of range." << endl;
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des->errors += 1;
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@@ -1558,7 +1558,8 @@ NetExpr* PEIdent::elaborate_expr_net_idx_do_(Design*des, NetScope*scope,
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// If the part select covers exactly the entire
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// vector, then do not bother with it. Return the
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// signal itself.
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if (net->sig()->sb_to_idx(lsv) == (wid-1) && wid == net->vector_width())
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if (net->sig()->sb_to_idx(lsv) == (signed) (wid-1) &&
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wid == net->vector_width())
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return net;
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// Otherwise, make a part select that covers the right range.
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