Support SystemVerilog net declaration assignments
SystemVerilog allows initialized and uninitialized net declaration entries to be mixed in the same declaration, e.g. `wire x, y = 1'b1`. In Verilog, either all nets need to have an initializer or non can have one. In addition SystemVerilog also allows assignments to arrays of wires during declaration. E.g. `wire a[3:0] = b;` Currently there are two different rules for net declarations, one for each of the Verilog variants. Combine these into a single rule to support SystemVerilog mixed declarations as well as the assignment to array nets. When running in Verilog mode still reject mixed initialized and uninitialized with a check after the parsing. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen
parent
e7934d5e66
commit
3495889112
128
parse.y
128
parse.y
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@ -101,6 +101,29 @@ static pform_name_t* pform_create_super(void)
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return res;
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}
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static void check_net_decl_assigns(const struct vlltype&loc,
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const std::list<decl_assignment_t*>*assign_list)
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{
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if (gn_system_verilog())
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return;
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bool has_initializer = false;
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bool has_no_initializer = false;
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for (const auto*cur : *assign_list) {
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if (cur->expr)
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has_initializer = true;
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else
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has_no_initializer = true;
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if (has_initializer && has_no_initializer) {
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pform_requires_sv(loc, "Mixing initialized and uninitialized "
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"net declaration entries");
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return;
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}
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}
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}
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/* The rules sometimes push attributes into a global context where
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sub-rules may grab them. This makes parser rules a little easier to
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write in some cases. */
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@ -720,9 +743,6 @@ Module::port_t *module_declare_interface_port(const YYLTYPE&loc, char *type,
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%type <wires> udp_port_decl udp_port_decls
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%type <statement> udp_initial udp_init_opt
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%type <wire> net_variable
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%type <wires> net_variable_list
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%type <text> event_variable label_opt class_declaration_endlabel_opt
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%type <text> block_identifier_opt
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%type <text> identifier_name
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@ -731,9 +751,6 @@ Module::port_t *module_declare_interface_port(const YYLTYPE&loc, char *type,
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%type <perm_strings> loop_variables
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%type <port_list> list_of_port_identifiers list_of_variable_port_identifiers
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%type <decl_assignments> net_decl_assigns
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%type <decl_assignment> net_decl_assign
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%type <mport> port port_opt port_reference port_reference_list
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%type <mport> port_declaration
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%type <mports> list_of_ports module_port_list_opt list_of_port_declarations module_attribute_foreign
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@ -780,7 +797,7 @@ Module::port_t *module_declare_interface_port(const YYLTYPE&loc, char *type,
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%type <expr> assignment_pattern expression expression_opt expr_mintypmax
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%type <expr> expr_primary_or_typename expr_primary
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%type <expr> class_new dynamic_array_new
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%type <expr> var_decl_initializer_opt initializer_opt
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%type <expr> net_decl_initializer_opt var_decl_initializer_opt initializer_opt
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%type <expr> inc_or_dec_expression inside_expression lpvalue
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%type <expr> branch_probe_expression streaming_concatenation
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%type <expr> delay_value delay_value_simple
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@ -788,8 +805,8 @@ Module::port_t *module_declare_interface_port(const YYLTYPE&loc, char *type,
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%type <exprs> expression_list_with_nuls expression_list_proper
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%type <exprs> cont_assign cont_assign_list
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%type <decl_assignment> variable_decl_assignment
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%type <decl_assignments> list_of_variable_decl_assignments
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%type <decl_assignment> net_decl_assign variable_decl_assignment
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%type <decl_assignments> net_decl_assigns list_of_variable_decl_assignments
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%type <data_type> data_type data_type_opt data_type_or_implicit data_type_or_implicit_or_void
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%type <data_type> data_type_or_implicit_no_opt
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@ -4983,70 +5000,30 @@ module_item
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/* Modules can contain further sub-module definitions. */
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: module
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| attribute_list_opt net_type data_type_or_implicit delay3_opt net_variable_list ';'
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{ data_type_t*data_type = $3;
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pform_check_net_data_type(@2, $2, $3);
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if (data_type == 0) {
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data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
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FILE_NAME(data_type, @2);
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}
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pform_set_data_type(@2, data_type, $5, $2, $1);
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if ($4 != 0) {
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yyerror(@2, "sorry: Net delays not supported.");
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delete $4;
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}
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delete $1;
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}
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| attribute_list_opt K_wreal delay3 net_variable_list ';'
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{ real_type_t*tmpt = new real_type_t(real_type_t::REAL);
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pform_set_data_type(@2, tmpt, $4, NetNet::WIRE, $1);
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if ($3 != 0) {
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yyerror(@3, "sorry: Net delays not supported.");
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delete $3;
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}
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delete $1;
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}
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| attribute_list_opt K_wreal net_variable_list ';'
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{ real_type_t*tmpt = new real_type_t(real_type_t::REAL);
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pform_set_data_type(@2, tmpt, $3, NetNet::WIRE, $1);
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delete $1;
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}
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/* Very similar to the rule above, but this takes a list of
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net_decl_assigns, which are <name> = <expr> assignment
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declarations. */
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| attribute_list_opt net_type data_type_or_implicit delay3_opt net_decl_assigns ';'
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{ data_type_t*data_type = $3;
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pform_check_net_data_type(@2, $2, $3);
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if (data_type == 0) {
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data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
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FILE_NAME(data_type, @2);
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}
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pform_makewire(@2, $4, str_strength, $5, $2, data_type, $1);
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delete $1;
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}
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/* This form doesn't have the range, but does have strengths. This
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gives strength to the assignment drivers. */
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| attribute_list_opt net_type drive_strength data_type_or_implicit net_decl_assigns ';'
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| attribute_list_opt net_type drive_strength_opt data_type_or_implicit delay3_opt net_decl_assigns ';'
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{ data_type_t*data_type = $4;
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pform_check_net_data_type(@2, $2, $4);
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check_net_decl_assigns(@6, $6);
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if (data_type == 0) {
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data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
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FILE_NAME(data_type, @2);
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}
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pform_makewire(@2, 0, $3, $5, $2, data_type, $1);
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pform_makewire(@2, $5, $3, $6, $2, data_type, $1);
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delete $1;
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}
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| attribute_list_opt K_wreal net_decl_assigns ';'
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| attribute_list_opt K_wreal delay3_opt net_decl_assigns ';'
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{ real_type_t*data_type = new real_type_t(real_type_t::REAL);
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pform_makewire(@2, 0, str_strength, $3, NetNet::WIRE, data_type, $1);
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check_net_decl_assigns(@4, $4);
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if ($3) {
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yyerror(@2, "error: wreal net does not support delay.");
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delete $3;
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}
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pform_makewire(@2, 0, str_strength, $4, NetNet::WIRE, data_type, $1);
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delete $1;
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}
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@ -5550,10 +5527,21 @@ generate_block
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Note that the continuous assignment statement is generated as a
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side effect, and all I pass up is the name of the l-value. */
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net_decl_initializer_opt
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: '=' expression { $$ = $2; }
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| { $$ = 0; }
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;
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net_decl_assign
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: IDENTIFIER '=' expression
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: IDENTIFIER dimensions_opt net_decl_initializer_opt
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{ decl_assignment_t*tmp = new decl_assignment_t;
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tmp->name = { lex_strings.make($1), @1.lexical_pos };
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if ($2) {
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tmp->index = *$2;
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if ($3)
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pform_requires_sv(@$, "Assignment of net array during declaration");
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delete $2;
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}
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tmp->expr.reset($3);
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delete[]$1;
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$$ = tmp;
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@ -6026,26 +6014,6 @@ dimensions
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}
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;
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net_variable
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: IDENTIFIER dimensions_opt
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{ pform_ident_t name = { lex_strings.make($1), @1.lexical_pos };
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$$ = pform_makewire(@1, name, NetNet::IMPLICIT, $2);
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delete [] $1;
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}
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;
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net_variable_list
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: net_variable
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{ std::vector<PWire*> *tmp = new std::vector<PWire*>;
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tmp->push_back($1);
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$$ = tmp;
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}
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| net_variable_list ',' net_variable
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{ $1->push_back($3);
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$$ = $1;
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}
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;
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event_variable
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: IDENTIFIER dimensions_opt
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{ if ($2) {
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12
pform.cc
12
pform.cc
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@ -49,6 +49,10 @@
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using namespace std;
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static void pform_set_data_type(const struct vlltype&li, data_type_t*data_type,
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std::vector<PWire*> *wires, NetNet::Type net_type,
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list<named_pexpr_t>*attr, bool is_const = false);
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/*
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* The "// synthesis translate_on/off" meta-comments cause this flag
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* to be turned off or on. The pform_make_behavior and similar
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@ -2724,6 +2728,8 @@ void pform_makewire(const struct vlltype&li,
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PGAssign*ass = pform_make_pgassign(lval, expr, delay, str);
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FILE_NAME(ass, li);
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}
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} else if (delay) {
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VLerror(li, "sorry: net delays not supported.");
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}
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delete first;
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}
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@ -3272,9 +3278,9 @@ void pform_set_port_type(const struct vlltype&li,
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* This function detects the derived class for the given type and
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* dispatches the type to the proper subtype function.
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*/
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void pform_set_data_type(const struct vlltype&li, data_type_t*data_type,
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std::vector<PWire*> *wires, NetNet::Type net_type,
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list<named_pexpr_t>*attr, bool is_const)
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static void pform_set_data_type(const struct vlltype&li, data_type_t*data_type,
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std::vector<PWire*> *wires, NetNet::Type net_type,
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list<named_pexpr_t>*attr, bool is_const)
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{
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if (data_type == 0) {
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VLerror(li, "internal error: data_type==0.");
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7
pform.h
7
pform.h
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@ -384,13 +384,6 @@ extern void pform_set_port_type(const struct vlltype&li,
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data_type_t*dt,
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std::list<named_pexpr_t>*attr);
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extern void pform_set_data_type(const struct vlltype&li,
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data_type_t *data_type,
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std::vector<PWire*> *wires,
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NetNet::Type net_type,
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std::list<named_pexpr_t>*attr,
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bool is_const = false);
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extern void pform_set_string_type(const struct vlltype&li, const string_type_t*string_type, std::list<perm_string>*names, NetNet::Type net_type, std::list<named_pexpr_t>*attr);
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extern void pform_set_class_type(const struct vlltype&li, class_type_t*class_type, std::list<perm_string>*names, NetNet::Type net_type, std::list<named_pexpr_t>*addr);
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