Add regression test for SystemVerilog task port types

Check that it is possible to declare task ports with SystemVerilog types.
Both ANSI style and one for non-ANSI style.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/task_port_types1.v

@@ -0,0 +1,35 @@
+// Check that it is possible to use SV data types for ANSI style task ports
+
+module test;
+
+  typedef logic [7:0] T1;
+  typedef struct packed { int i; } T2;
+  typedef enum { A } T3;
+
+  task t(input reg a,
+         input logic b,
+         input bit c,
+         input logic [3:0] d,
+         input bit [3:0][3:0] e,
+         input byte f,
+         input int g,
+         input T1 h,
+         input T2 i,
+         input T3 j,
+         input real k,
+         input shortreal l,
+         input string m,
+         input int n[],
+         input int o[$],
+         input x,
+         input [3:0] y,
+         input signed z
+  );
+    $display("PASSED");
+  endtask
+
+  initial begin
+    t('0, '0, '0, '0, '0, '0, '0, '0, '0, A, 0.0, 0.0, "", '{0}, '{0}, '0, '0, '0);
+  end
+
+endmodule

ivtest/ivltests/task_port_types2.v

@@ -0,0 +1,35 @@
+// Check that it is possible to use SV data types for non-ANSI style task ports
+
+module test;
+
+  typedef logic [7:0] T1;
+  typedef struct packed { int i; } T2;
+  typedef enum { A } T3;
+
+  task t;
+  input reg a;
+  input logic b;
+  input bit c;
+  input logic [3:0] d;
+  input bit [3:0][3:0] e;
+  input byte f;
+  input int g;
+  input T1 h;
+  input T2 i;
+  input T3 j;
+  input real k;
+  input shortreal l;
+  input string m;
+  input int n[];
+  input int o[$];
+  input x;
+  input [3:0] y;
+  input signed z;
+    $display("PASSED");
+  endtask
+
+  initial begin
+    t('0, '0, '0, '0, '0, '0, '0, '0, '0, A, 0.0, 0.0, "", '{0}, '{0}, '0, '0, '0);
+  end
+
+endmodule

ivtest/regress-sv.list

@@ -580,6 +580,8 @@ task_init_assign	normal,-g2009		ivltests
 task_init_var1		normal,-g2009		ivltests
 task_init_var2		normal,-g2009		ivltests
 task_init_var3		normal,-g2009		ivltests
+task_port_types1	normal,-g2009		ivltests
+task_port_types2	normal,-g2009		ivltests
 task_scope2		normal,-g2009		ivltests
 test_inc_dec		normal,-g2009		ivltests
 test_tliteral		normal,-g2009		ivltests

ivtest/regress-vlog95.list

@@ -95,6 +95,8 @@ recursive_task		CE			ivltests
 task_init_var1		CE,-pallowsigned=1	ivltests
 task_init_var2		CE,-pallowsigned=1	ivltests
 task_init_var3		CE,-pallowsigned=1	ivltests
+task_port_types1	CE,-pallowsigned=1	ivltests
+task_port_types2	CE,-pallowsigned=1	ivltests
 test_work14		CE			ivltests
 vhdl_elab_range		CE			ivltests
 vhdl_notfunc_stdlogic	CE			ivltests