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Emit net declarations. 

Rather then leave net types to implicit declarations, write
declarations explicitly. This will become necessary when more
interesting types are supported.
This commit is contained in:
Stephen Williams 2011-02-02 21:15:46 -08:00
parent d8d56bc569
commit b08ab3448e
3 changed files with 63 additions and 11 deletions
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10
vhdlpp/entity.h
View File

@ -73,8 +73,16 @@ class Entity : public LineInfo {
std::vector<InterfacePort*> ports_;
std::map<perm_string,Architecture*>arch_;
Architecture*bind_arch_;
enum vtype_t { VNONE, VUWIRE };
struct decl_t {
vtype_t type;
long msb, lsb;
};
map<perm_string,decl_t> declarations_;
int elaborate_ports_(void);
};
/*

37
vhdlpp/entity_elaborate.cc
View File

@ -23,6 +23,7 @@
# include <iostream>
# include <fstream>
# include <iomanip>
# include <cstring>
using namespace std;
@ -72,5 +73,41 @@ int Entity::elaborate()
<< ", choosing architecture " << bind_arch_->get_name()
<< "." << endl;
errors += elaborate_ports_();
return errors;
}
int Entity::elaborate_ports_(void)
{
int errors = 0;
for (std::vector<InterfacePort*>::const_iterator cur = ports_.begin()
; cur != ports_.end() ; ++cur) {
InterfacePort*cur_port = *cur;
decl_t cur_decl;
cur_decl.type = VNONE;
cur_decl.msb = 0;
cur_decl.lsb = 0;
if (strcasecmp(cur_port->type_name, "std_logic") == 0) {
cur_decl.type = VUWIRE;
} else if (strcasecmp(cur_port->type_name, "bit") == 0) {
cur_decl.type = VUWIRE;
} else if (strcasecmp(cur_port->type_name, "boolean") == 0) {
cur_decl.type = VUWIRE;
} else {
cerr << get_fileline() << ": error: "
<< "I don't know how to map port " << cur_port->name
<< " type " << cur_port->type_name << "." << endl;
errors += 1;
}
declarations_[cur_port->name] = cur_decl;
}
return errors;
}

27
vhdlpp/entity_emit.cc
View File

@ -49,16 +49,6 @@ int Entity::emit(ostream&out)
; cur != ports_.end() ; ++cur) {
InterfacePort*port = *cur;
// FIXME: this is a stub. This port handling code
// currently only supports std_logic signal tyes,
// so just assert that the user asked for std_logic.
if (port->type_name != "std_logic") {
cerr << "sorry: VHDL only supports std_logic ports."
<< " Expecting std_logic, but got \""
<< port->type_name << "\"" << endl;
errors += 1;
}
if (sep) out << sep;
else sep = ", ";
@ -79,6 +69,23 @@ int Entity::emit(ostream&out)
out << ";" << endl;
for (map<perm_string,decl_t>::const_iterator cur = declarations_.begin()
; cur != declarations_.end() ; ++cur) {
switch (cur->second.type) {
case VNONE:
out << "// N type for " << cur->first << endl;
break;
case VUWIRE:
out << "wire ";
if (cur->second.msb != cur->second.lsb)
out << "[" << cur->second.msb
<< ":" << cur->second.lsb << "] ";
out << cur->first << ";" << endl;
break;
}
}
errors += bind_arch_->emit(out, this);
out << "endmodule" << endl;