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Fix some cppcheck warnings in the main directory

This commit is contained in:
Cary R 2012-08-08 11:26:46 -07:00
parent 429babf831
commit 7ce8a9b01c
11 changed files with 32 additions and 33 deletions
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10
HName.cc
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2001-2010 Stephen Williams (steve@icarus.com)
* Copyright (c) 2001-2012 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@ -31,21 +31,19 @@ hname_t::hname_t()
}
hname_t::hname_t(perm_string text)
: name_(text)
{
name_ = text;
number_ = INT_MIN;
}
hname_t::hname_t(perm_string text, int num)
: name_(text), number_(num)
{
name_ = text;
number_ = num;
}
hname_t::hname_t(const hname_t&that)
: name_(that.name_), number_(that.number_)
{
name_ = that.name_;
number_ = that.number_;
}
hname_t& hname_t::operator = (const hname_t&that)

2
Makefile.in
View File

@ -87,7 +87,7 @@ GIT = @GIT@
ifeq (@srcdir@,.)
INCLUDE_PATH = -I. -Ilibmisc
else
INCLUDE_PATH = -I. -Ilibmisc -I$(srcdir) -I$(srcdir)/libmisc
INCLUDE_PATH = -I. -I$(srcdir) -I$(srcdir)/libmisc
endif
CPPFLAGS = @DEFS@ $(INCLUDE_PATH) @CPPFLAGS@

6
design_dump.cc
View File

@ -261,7 +261,7 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
if (netdarray_t*darray = darray_type())
o << " dynamic array of " << darray->data_type();
if (!packed_dims_.empty())
if (! packed_dims_.empty())
o << " packed dims: " << packed_dims_;
o << " (eref=" << peek_eref() << ", lref=" << peek_lref() << ")";
@ -1305,7 +1305,7 @@ void NetSTask::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << name_;
if (parms_.size() > 0) {
if (! parms_.empty()) {
o << "(";
if (parms_[0])
parms_[0]->dump(o);
@ -1545,7 +1545,7 @@ void NetETernary::dump(ostream&o) const
void NetEUFunc::dump(ostream&o) const
{
o << func_->basename() << "(";
if (parms_.size() > 0) {
if (! parms_.empty()) {
parms_[0]->dump(o);
for (unsigned idx = 1 ; idx < parms_.size() ; idx += 1) {
o << ", ";

2
elab_lval.cc
View File

@ -721,7 +721,7 @@ bool PEIdent::elaborate_lval_net_packed_member_(Design*des, NetScope*scope,
ivl_assert(*this, use_sel == index_component_t::SEL_NONE || use_sel == index_component_t::SEL_BIT);
if (name_tail.index.size() > 0) {
if (! name_tail.index.empty()) {
// Evaluate all but the last index expression, into prefix_indices.
list<long>prefix_indices;
bool rc = evaluate_index_prefix(des, scope, prefix_indices, name_tail.index);

4
net_design.cc
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2011 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2012 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@ -197,7 +197,7 @@ NetScope* Design::find_scope(NetScope*scope, const std::list<hname_t>&path,
if (cur == 0) break;
}
tmp.pop_front();
} while (!tmp.empty());
} while (! tmp.empty());
if (cur) return cur;
}

2
net_nex_input.cc
View File

@ -397,7 +397,7 @@ NexusSet* NetRepeat::nex_input(bool rem_out)
*/
NexusSet* NetSTask::nex_input(bool rem_out)
{
if (parms_.size() == 0)
if (parms_.empty())
return new NexusSet;
NexusSet*result;

2
net_scope.cc
View File

@ -370,7 +370,7 @@ perm_string NetScope::module_name() const
void NetScope::set_num_ports(unsigned int num_ports)
{
assert(type_ == MODULE);
assert( ports_.size() == 0 );
assert(ports_.empty());
ports_.resize( num_ports );
}

2
netlist.cc
View File

@ -918,7 +918,7 @@ unsigned NetNet::peek_eref() const
*/
bool NetNet::test_part_lref(unsigned pmsb, unsigned plsb)
{
if (lref_mask_.size() == 0)
if (lref_mask_.empty())
lref_mask_.resize(vector_width());
bool rc = false;

2
nettypes.cc
View File

@ -71,7 +71,7 @@ bool prefix_to_slice(const std::list<netrange_t>&dims,
else
acc_off += (sb - pcur->get_msb()) * acc_wid;
if (prefix.size() == 0) {
if (prefix.empty()) {
loff = acc_off;
return true;
}

29
pform.cc
View File

@ -408,7 +408,7 @@ void pform_bind_attributes(map<perm_string,PExpr*>&attributes,
bool pform_in_program_block()
{
if (pform_cur_module.size() == 0)
if (pform_cur_module.empty())
return false;
if (pform_cur_module.front()->program_block)
return true;
@ -494,7 +494,7 @@ void pform_set_default_nettype(NetNet::Type type,
{
pform_default_nettype = type;
if (pform_cur_module.size() > 0) {
if (! pform_cur_module.empty()) {
cerr << file<<":"<<lineno << ": error: "
<< "`default_nettype directives must appear" << endl;
cerr << file<<":"<<lineno << ": : "
@ -814,13 +814,14 @@ verinum* pform_verinum_with_size(verinum*siz, verinum*val,
void pform_startmodule(const struct vlltype&loc, const char*name,
bool program_block, list<named_pexpr_t>*attr)
{
if (pform_cur_module.size() > 0 && !gn_system_verilog()) {
if (! pform_cur_module.empty() && !gn_system_verilog()) {
cerr << loc << ": error: Module definition " << name
<< " cannot nest into module " << pform_cur_module.front()->mod_name() << "." << endl;
error_count += 1;
}
if (gn_system_verilog() && pform_cur_module.size() > 0 && pform_cur_module.front()->program_block) {
if (gn_system_verilog() && ! pform_cur_module.empty() &&
pform_cur_module.front()->program_block) {
cerr << loc << ": error: Program blocks cannot contain nested modules/program blocks." << endl;
error_count += 1;
}
@ -868,7 +869,7 @@ void pform_startmodule(const struct vlltype&loc, const char*name,
*/
void pform_check_timeunit_prec()
{
assert(pform_cur_module.size() > 0);
assert(! pform_cur_module.empty());
if ((generation_flag & (GN_VER2005_SV | GN_VER2009)) &&
(pform_cur_module.front()->time_unit < pform_cur_module.front()->time_precision)) {
VLerror("error: a timeprecision is missing or is too large!");
@ -896,7 +897,7 @@ Module::port_t* pform_module_port_reference(perm_string name,
void pform_module_set_ports(vector<Module::port_t*>*ports)
{
assert(pform_cur_module.size() > 0);
assert(! pform_cur_module.empty());
/* The parser parses ``module foo()'' as having one
unconnected port, but it is really a module with no
@ -915,7 +916,7 @@ void pform_module_set_ports(vector<Module::port_t*>*ports)
void pform_endmodule(const char*name, bool inside_celldefine,
Module::UCDriveType uc_drive_def)
{
assert(pform_cur_module.size() > 0);
assert(! pform_cur_module.empty());
Module*cur_module = pform_cur_module.front();
pform_cur_module.pop_front();
@ -931,7 +932,7 @@ void pform_endmodule(const char*name, bool inside_celldefine,
// root list of modules. Otherwise, this is a nested module
// and we put it into the parent module scope to be elaborated
// if needed.
map<perm_string,Module*>&use_module_map = (pform_cur_module.size() == 0)
map<perm_string,Module*>&use_module_map = (pform_cur_module.empty())
? pform_modules
: pform_cur_module.front()->nested_modules;
@ -951,7 +952,7 @@ void pform_endmodule(const char*name, bool inside_celldefine,
// this module should not have a parent lexical scope.
ivl_assert(*cur_module, lexical_scope == cur_module);
pform_pop_scope();
ivl_assert(*cur_module, pform_cur_module.size()>0 || lexical_scope == 0);
ivl_assert(*cur_module, ! pform_cur_module.empty() || lexical_scope == 0);
tp_decl_flag = false;
tu_decl_flag = false;
@ -1138,7 +1139,7 @@ void pform_generate_block_name(char*name)
void pform_endgenerate()
{
assert(pform_cur_generate != 0);
assert(pform_cur_module.size() > 0);
assert(! pform_cur_module.empty());
// If there is no explicit block name then generate a temporary
// name. This will be replaced by the correct name later, once
@ -1688,7 +1689,7 @@ void pform_makegates(const struct vlltype&loc,
svector<lgate>*gates,
list<named_pexpr_t>*attr)
{
assert(pform_cur_module.size() > 0);
assert(! pform_cur_module.empty());
if (pform_cur_module.front()->program_block) {
cerr << loc << ": error: Gates and switches may not be instantiated"
<< " in program blocks." << endl;
@ -1804,7 +1805,7 @@ void pform_make_modgates(const struct vlltype&loc,
struct parmvalue_t*overrides,
svector<lgate>*gates)
{
assert(pform_cur_module.size() > 0);
assert(! pform_cur_module.empty());
if (pform_cur_module.front()->program_block) {
cerr << loc << ": error: Module instantiations are not allowed"
<< " in program blocks." << endl;
@ -2528,7 +2529,7 @@ void pform_set_localparam(const struct vlltype&loc,
void pform_set_specparam(const struct vlltype&loc, perm_string name,
list<pform_range_t>*range, PExpr*expr)
{
assert(pform_cur_module.size() > 0);
assert(! pform_cur_module.empty());
Module*scope = pform_cur_module.front();
assert(scope == lexical_scope);
@ -2908,7 +2909,7 @@ PProcess* pform_make_behavior(ivl_process_type_t type, Statement*st,
pform_put_behavior_in_scope(pp);
ivl_assert(*st, pform_cur_module.size() > 0);
ivl_assert(*st, ! pform_cur_module.empty());
if (pform_cur_module.front()->program_block && type == IVL_PR_ALWAYS) {
cerr << st->get_fileline() << ": error: Always statements not allowed"
<< " in program blocks." << endl;

4
t-dll-api.cc
View File

@ -2207,7 +2207,7 @@ extern "C" int ivl_signal_packed_lsb(ivl_signal_t net, unsigned dim)
extern "C" int ivl_signal_msb(ivl_signal_t net)
{
if (net->packed_dims.size() == 0)
if (net->packed_dims.empty())
return 0;
assert(net->packed_dims.size() == 1);
@ -2216,7 +2216,7 @@ extern "C" int ivl_signal_msb(ivl_signal_t net)
extern "C" int ivl_signal_lsb(ivl_signal_t net)
{
if (net->packed_dims.size() == 0)
if (net->packed_dims.empty())
return 0;
assert(net->packed_dims.size() == 1);