Stub file for processing statements

tgt-vhdl/process.cc

@@ -33,6 +33,11 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
 {
    vhdl_process *vhdl_proc = new vhdl_process();
 
+   ivl_statement_t stmt = ivl_process_stmt(proc);
+   int rc = draw_stmt(vhdl_proc, stmt);
+   if (rc != 0)
+      return rc;
+   
    // Initial processes are translated to VHDL processes with
    // no sensitivity list and and indefinite wait statement at
    // the end

tgt-vhdl/stmt.cc

@@ -0,0 +1,32 @@
+/*
+ *  VHDL code generation for statements.
+ *
+ *  Copyright (C) 2008  Nick Gasson (nick@nickg.me.uk)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "vhdl_target.h"
+
+#include <iostream>
+
+/*
+ * Generate VHDL statements for the given Verilog statement and
+ * add them to the given VHDL process.
+ */
+int draw_stmt(vhdl_process *proc, ivl_statement_t stmt)
+{
+   return 0;
+}

tgt-vhdl/vhdl_target.h

@@ -12,6 +12,7 @@ void error(const char *fmt, ...);
 
 int draw_scope(ivl_scope_t scope, void *_parent);
 int draw_process(ivl_process_t net, void *cd);
+int draw_stmt(vhdl_process *proc, ivl_statement_t stmt);
 
 void remember_entity(vhdl_entity *ent);
 vhdl_entity *find_entity(const std::string &tname);