Add regression tests for early signal elaboration.

ivtest/gold/early_sig_elab3-iverilog-stderr.gold

@@ -0,0 +1,2 @@
+ivltests/early_sig_elab3.v:8: error: Circular dependency detected in declaration of 'a'.
+1 error(s) during elaboration.

ivtest/ivltests/br_gh1097.v

@@ -0,0 +1,18 @@
+module test_mod ();
+ 
+    typedef enum logic [4:0] {ENUM_ELEM1, ENUM_ELEM2} test_enum_t;
+
+    test_enum_t test_mem_addr_e;
+    logic [1:0] test_mem [test_mem_addr_e.num()];
+
+    initial begin
+        test_mem[ENUM_ELEM1] = 1;
+        test_mem[ENUM_ELEM2] = 2;
+        $display("ENUM_ELEM1 = %d test_mem[ENUM_ELEM1] = %d", ENUM_ELEM1, test_mem[ENUM_ELEM1]);
+        $display("ENUM_ELEM2 = %d test_mem[ENUM_ELEM2] = %d", ENUM_ELEM2, test_mem[ENUM_ELEM2]);
+        if (test_mem[ENUM_ELEM1] === 1 && test_mem[ENUM_ELEM2] === 2)
+            $display("PASSED");
+        else
+            $display("FAILED");
+    end
+endmodule 

ivtest/ivltests/br_gh483a.v

@@ -0,0 +1,21 @@
+// Strictly speaking this is illegal as it uses a hierarchical name in a
+// constant expression.
+module top;
+    parameter ENABLE = 1;
+    if (ENABLE) begin : blk
+        wire [7:0] w;
+    end
+    wire [7:0] x;
+    wire [$bits(blk.w)-1:0] y = 8'h55;
+    wire [$bits(x)-1:0] z = 8'haa;
+    initial begin
+        $display("blk.w: %b (%0d bits)", blk.w, $bits(blk.w));
+        $display("x: %b (%0d bits)", x, $bits(x));
+        $display("y: %b (%0d bits)", y, $bits(y));
+        $display("z: %b (%0d bits)", z, $bits(z));
+        if (y === 8'h55 && z === 8'haa)
+            $display("PASSED");
+        else
+            $display("FAILED");
+    end
+endmodule

ivtest/ivltests/br_gh483b.v

@@ -0,0 +1,18 @@
+module Module;
+    parameter T = 10;
+    wire [T-1:0] x = 8'h55;
+    initial $display("Module %b %0d", x, T);
+endmodule
+
+module top;
+    wire [7:0] x;
+    Module #($bits(x)) mA();
+    Module #(8) mB();
+
+    initial begin
+        if (mA.x === 8'h55 && mB.x === 8'h55)
+            $display("PASSED");
+        else
+            $display("FAILED");
+    end
+endmodule

ivtest/ivltests/early_sig_elab1.v

@@ -0,0 +1,25 @@
+// Icarus elaborates signals in alphabetical order, so force early
+// elaboration that way.
+
+module test;
+
+localparam LSB = 0;
+localparam MSB = 7;
+
+reg [MSB:LSB] c;
+reg [$bits(c):1] a;
+
+localparam WIDTH = $bits(c);
+
+reg [WIDTH:1] b;
+
+initial begin
+  $display("a = %b", a);
+  $display("b = %b", b);
+  if ($bits(a) === 8 && $bits(b) == 8)
+    $display("PASSED");
+  else
+    $display("FAILED");
+end
+
+endmodule

ivtest/ivltests/early_sig_elab2.v

@@ -0,0 +1,27 @@
+// Strictly speaking this is not legal as it uses a hierarchical name in a
+// constant expression,
+
+module test1;
+
+reg [$bits(test2.v):1] v;
+
+endmodule
+
+module test2;
+
+reg [7:0] v;
+
+initial begin
+  if ($bits(test1.v) === 8 && $bits(test3.v) === 8)
+    $display("PASSED");
+  else
+    $display("FAILED");
+end
+
+endmodule
+
+module test3;
+
+reg [$bits(test2.v):1] v;
+
+endmodule

ivtest/ivltests/early_sig_elab3.v

@@ -0,0 +1,16 @@
+// Test we detect and report circular dependencies.
+
+// Strictly speaking this is not legal as it uses a hierarchical name in a
+// constant expression,
+
+module test;
+
+reg [$bits(test.b):1] a;
+reg [$bits(test.a):1] b;
+
+initial begin
+  // This test is expected to fail at compile time.
+  $display("FAILED");
+end
+
+endmodule

ivtest/regress-vvp.list

@@ -25,6 +25,8 @@ br_gh383b			vvp_tests/br_gh383b.json
 br_gh383c			vvp_tests/br_gh383c.json
 br_gh383d			vvp_tests/br_gh383d.json
 br_gh440			vvp_tests/br_gh440.json
+br_gh483a			vvp_tests/br_gh483a.json
+br_gh483b			vvp_tests/br_gh483b.json
 br_gh552			vvp_tests/br_gh552.json
 br_gh687			vvp_tests/br_gh687.json
 br_gh703			vvp_tests/br_gh703.json
@@ -42,6 +44,7 @@ br_gh1087a2			vvp_tests/br_gh1087a2.json
 br_gh1087a3			vvp_tests/br_gh1087a3.json
 br_gh1087b			vvp_tests/br_gh1087b.json
 br_gh1087c			vvp_tests/br_gh1087c.json
+br_gh1097			vvp_tests/br_gh1097.json
 br_gh1099a			vvp_tests/br_gh1099a.json
 br_gh1099b			vvp_tests/br_gh1099b.json
 br_gh1099c			vvp_tests/br_gh1099c.json
@@ -84,6 +87,9 @@ dffsynth9			vvp_tests/dffsynth9.json
 dffsynth10			vvp_tests/dffsynth10.json
 dffsynth11			vvp_tests/dffsynth11.json
 dumpfile			vvp_tests/dumpfile.json
+early_sig_elab1			vvp_tests/early_sig_elab1.json
+early_sig_elab2			vvp_tests/early_sig_elab2.json
+early_sig_elab3			vvp_tests/early_sig_elab3.json
 eofmt_percent			vvp_tests/eofmt_percent.json
 eofmt_percent-vlog95		vvp_tests/eofmt_percent-vlog95.json
 fdisplay3			vvp_tests/fdisplay3.json

ivtest/vvp_tests/br_gh1097.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "br_gh1097.v",
+    "iverilog-args" : [ "-g2009" ]
+}

ivtest/vvp_tests/br_gh483a.json

@@ -0,0 +1,4 @@
+{
+    "type"   : "normal",
+    "source" : "br_gh483a.v"
+}

ivtest/vvp_tests/br_gh483b.json

@@ -0,0 +1,4 @@
+{
+    "type"   : "normal",
+    "source" : "br_gh483b.v"
+}

ivtest/vvp_tests/early_sig_elab1.json

@@ -0,0 +1,4 @@
+{
+    "type"   : "normal",
+    "source" : "early_sig_elab1.v"
+}

ivtest/vvp_tests/early_sig_elab2.json

@@ -0,0 +1,4 @@
+{
+    "type"   : "normal",
+    "source" : "early_sig_elab2.v"
+}

ivtest/vvp_tests/early_sig_elab3.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "CE",
+    "source" : "early_sig_elab3.v",
+    "gold"   : "early_sig_elab3"
+}