luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Make MUXZ and MUXR use enum for select type. 

Rework the MUXZ and MUXR code to use an enum instead of plain
integers for the select input state. This makes it more obvious
what is actually going on.
This commit is contained in:
Cary R 2008-04-08 09:17:51 -07:00 committed by Stephen Williams
parent fecd941a28
commit 44767d8f70
2 changed files with 26 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
vvp/logic.cc
View File

@ -258,7 +258,7 @@ vvp_fun_muxr::vvp_fun_muxr()
{
net_ = 0;
count_functors_logic += 1;
select_ = 2;
select_ = SEL_BOTH;
}
vvp_fun_muxr::~vvp_fun_muxr()
@ -276,16 +276,16 @@ void vvp_fun_muxr::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
switch (bit.value(0)) {
case BIT4_0:
if (select_ == 0) return;
select_ = 0;
if (select_ == SEL_PORT0) return;
select_ = SEL_PORT0;
break;
case BIT4_1:
if (select_ == 1) return;
select_ = 1;
if (select_ == SEL_PORT1) return;
select_ = SEL_PORT1;
break;
default:
if (select_ == 2) return;
select_ = 2;
if (select_ == SEL_BOTH) return;
select_ = SEL_BOTH;
}
if (net_ == 0) {
@ -300,13 +300,13 @@ void vvp_fun_muxr::recv_real(vvp_net_ptr_t ptr, double bit)
case 0:
if (a_ == bit) return;
a_ = bit;
if (select_ == 1) return; // The other port is selected.
if (select_ == SEL_PORT1) return; // The other port is selected.
break;
case 1:
if (b_ == bit) return;
b_ = bit;
if (select_ == 0) return; // The other port is selected.
if (select_ == SEL_PORT0) return; // The other port is selected.
break;
default:
@ -326,10 +326,10 @@ void vvp_fun_muxr::run_run()
net_ = 0;
switch (select_) {
case 0:
case SEL_PORT0:
vvp_send_real(ptr->out, a_);
break;
case 1:
case SEL_PORT1:
vvp_send_real(ptr->out, b_);
break;
default:
@ -347,7 +347,7 @@ vvp_fun_muxz::vvp_fun_muxz(unsigned wid)
{
net_ = 0;
count_functors_logic += 1;
select_ = 2;
select_ = SEL_BOTH;
has_run_ = false;
for (unsigned idx = 0 ; idx < wid ; idx += 1) {
a_.set_bit(idx, BIT4_X);
@ -365,27 +365,27 @@ void vvp_fun_muxz::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
case 0:
if (a_ .eeq(bit) && has_run_) return;
a_ = bit;
if (select_ == 1) return; // The other port is selected.
if (select_ == SEL_PORT1) return; // The other port is selected.
break;
case 1:
if (b_ .eeq(bit) && has_run_) return;
b_ = bit;
if (select_ == 0) return; // The other port is selected.
if (select_ == SEL_PORT0) return; // The other port is selected.
break;
case 2:
assert(bit.size() == 1);
switch (bit.value(0)) {
case BIT4_0:
if (select_ == 0) return;
select_ = 0;
if (select_ == SEL_PORT0) return;
select_ = SEL_PORT0;
break;
case BIT4_1:
if (select_ == 1) return;
select_ = 1;
if (select_ == SEL_PORT1) return;
select_ = SEL_PORT1;
break;
default:
if (select_ == 2 && has_run_) return;
select_ = 2;
if (select_ == SEL_BOTH && has_run_) return;
select_ = SEL_BOTH;
}
break;
default:
@ -405,10 +405,10 @@ void vvp_fun_muxz::run_run()
net_ = 0;
switch (select_) {
case 0:
case SEL_PORT0:
vvp_send_vec4(ptr->out, a_);
break;
case 1:
case SEL_PORT1:
vvp_send_vec4(ptr->out, b_);
break;
default:

6
vvp/logic.h
View File

@ -121,6 +121,8 @@ class vvp_fun_bufz: public vvp_net_fun_t {
private:
};
enum sel_type {SEL_PORT0, SEL_PORT1, SEL_BOTH};
/*
* The muxz functor is an A-B mux device, with the data inputs on
* ports 0 and 1. port 2 is the select input.
@ -146,8 +148,8 @@ class vvp_fun_muxz : public vvp_net_fun_t, private vvp_gen_event_s {
private:
vvp_vector4_t a_;
vvp_vector4_t b_;
int select_;
vvp_net_t*net_;
sel_type select_;
bool has_run_;
};
@ -166,8 +168,8 @@ class vvp_fun_muxr : public vvp_net_fun_t, private vvp_gen_event_s {
private:
double a_;
double b_;
int select_;
vvp_net_t*net_;
sel_type select_;
};
class vvp_fun_not: public vvp_net_fun_t, private vvp_gen_event_s {