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tgt-vvp: Use signedness of expression instead of signal for index load 

When loading a signal into into an index register currently the signedness
of the signal is used when deciding whether sign-extension should be
performed or not. But this can lead to incorrect results, instead the
signedness of the expression must be used as that might be different from
the signal. E.g.

```
reg signed [1:0] = 2'b10;
$display(1 << x[1:0]);
```

gives the wrong result without this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2024-09-02 18:25:41 +02:00
parent cbdaa865a1
commit 50d9a32d56
1 changed files with 1 additions and 2 deletions
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3
tgt-vvp/eval_expr.c
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@ -226,12 +226,12 @@ void eval_logic_into_integer(ivl_expr_t expr, unsigned ix)
reading index values directly from variables. In
this case, try to use that special instruction. */
case IVL_EX_SIGNAL: {
const char*type = ivl_expr_signed(expr) ? "/s" : "";
ivl_signal_t sig = ivl_expr_signal(expr);
unsigned word = 0;
if (ivl_signal_dimensions(sig) > 0) {
ivl_expr_t ixe;
const char*type = ivl_expr_signed(expr) ? "/s" : "";
/* Detect the special case that this is a
variable array. In this case, the ix/getv
@ -252,7 +252,6 @@ void eval_logic_into_integer(ivl_expr_t expr, unsigned ix)
break;
}
}
const char*type = ivl_signal_signed(sig) ? "/s" : "";
fprintf(vvp_out, " %%ix/getv%s %u, v%p_%u;\n", type, ix,
sig, word);
break;