luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix another case where VHDL input may be driven 

This fixes another corner case where the VHDL code generator
would incorrectly generate code that drives an input with an
output.
This commit is contained in:
Nick Gasson 2009-02-08 12:46:31 +00:00 committed by Stephen Williams
parent bb37607a30
commit a931eaa586
1 changed files with 2 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
tgt-vhdl/scope.cc
View File

@ -80,13 +80,11 @@ static void link_scope_to_nexus_signal(nexus_private_t *priv, vhdl_scope *scope,
scope_nexus_t *sn;
if ((sn = visible_nexus(priv, scope))) {
assert(sn->tmpname == "");
// Remember to connect this signal up later
// If one of the signals is a input, make sure the input is not being driven
if (ivl_signal_port(sn->sig) == IVL_SIP_INPUT) {
sn->connect.push_back(sn->sig);
if (ivl_signal_port(sn->sig) == IVL_SIP_INPUT)
sn->sig = sig;
}
else
sn->connect.push_back(sig);
}