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Allow inputs to be variables in SystemVerilog 

SystemVerilog allows input ports to be variables. If something is connected
to the input port it will be converted to an unresolved wire.

This is handled the same as having a continuous assignment on a
SystemVerilog varibale.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2022-05-22 16:38:42 +02:00
parent 0f7703e9c6
commit 246a0d3ce8
2 changed files with 11 additions and 2 deletions
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6
elab_sig.cc
View File

@ -144,10 +144,12 @@ static void sig_check_port_type(Design*des, NetScope*scope,
return;
/* If the signal is an input and is also declared as a
reg, then report an error. */
reg, then report an error. In SystemVerilog a input
is allowed to be a register. It will get converted
to a unresolved wire when the port is connected. */
if (sig->port_type() == NetNet::PINPUT &&
sig->type() == NetNet::REG) {
sig->type() == NetNet::REG && !gn_var_can_be_uwire()) {
cerr << wire->get_fileline() << ": error: Port `"
<< wire->basename() << "` of module `"
<< scope->module_name()

7
elaborate.cc
View File

@ -1533,6 +1533,13 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
delete tmp_expr;
if (!sig->get_lineno()) sig->set_line(*this);
if (ptype == NetNet::PINPUT && gn_var_can_be_uwire()) {
for (unsigned int i = 0; i < prts.size(); i++) {
if (prts[i]->type() == NetNet::REG)
prts[i]->type(NetNet::UNRESOLVED_WIRE);
}
}
if (need_bufz_for_input_port(prts)) {
NetBUFZ*tmp = new NetBUFZ(scope, scope->local_symbol(),
sig->vector_width(), true);