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Change VHDL $finish to use report not assert 

Changes:

   assert false report "SIMULATION FINISHED" severity failure;

To just:

   report "SIMULATION FINISHED" severity failure;
This commit is contained in:
Nick Gasson 2010-08-24 22:17:11 +01:00
parent a7fe5167e8
commit 249fc93b89
1 changed files with 3 additions and 1 deletions
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4
tgt-vhdl/stmt.cc
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@ -54,7 +54,9 @@ static int draw_stask_finish(vhdl_procedural *proc, stmt_container *container,
container->add_stmt(new vhdl_pcall_stmt("work.Verilog_Support.Finish"));
}
else {
container->add_stmt(new vhdl_assert_stmt("SIMULATION FINISHED"));
container->add_stmt(
new vhdl_report_stmt(new vhdl_const_string("SIMULATION FINISHED"),
SEVERITY_FAILURE));
}
return 0;