Island ports can accept vector parts.
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@ -124,6 +124,8 @@ class vvp_island_port : public vvp_net_fun_t {
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~vvp_island_port();
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virtual void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit);
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virtual void recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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unsigned base, unsigned wid, unsigned vwid);
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virtual void recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t bit);
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vvp_vector8_t invalue;
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@ -220,6 +222,7 @@ void vvp_island::add_branch(vvp_island_branch*branch, const char*pa, const char*
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assert(ports_);
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branch->a = ports_->sym_get_value(pa);
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branch->b = ports_->sym_get_value(pb);
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assert(branch->a && branch->b);
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vvp_branch_ptr_t ptra (branch, 0);
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vvp_branch_ptr_t ptrb (branch, 1);
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@ -286,6 +289,26 @@ void vvp_island_port::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit)
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recv_vec8(port, vvp_vector8_t(bit, 6, 6));
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}
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void vvp_island_port::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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unsigned base, unsigned wid, unsigned vwid)
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{
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vvp_vector8_t tmp(bit, 6, 6);
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if (invalue.size()==0) {
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assert(tmp.size() == wid);
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invalue = part_expand(tmp, vwid, base);
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} else {
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assert(invalue.size() == vwid);
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for (unsigned idx = 0 ; idx < wid ; idx += 1) {
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if ((base+idx) >= invalue.size())
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break;
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invalue.set_bit(base+idx, tmp.value(idx));
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}
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}
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island_->flag_island();
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}
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void vvp_island_port::recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t bit)
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{
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invalue = bit;
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@ -1802,6 +1802,10 @@ vvp_vector8_t::vvp_vector8_t(const vvp_vector4_t&that,
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vvp_vector8_t& vvp_vector8_t::operator= (const vvp_vector8_t&that)
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{
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// Assign to self.
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if (size_ > 0 && bits_ == that.bits_)
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return *this;
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if (size_ != that.size_) {
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if (size_ > 0)
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delete[]bits_;
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@ -1845,7 +1849,7 @@ vvp_vector8_t vvp_vector8_t::subvalue(unsigned base, unsigned wid) const
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vvp_vector8_t tmp (wid);
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unsigned idx = 0;
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while (base+idx < size_) {
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while (idx < wid && base+idx < size_) {
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tmp.bits_[idx] = bits_[base+idx];
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idx += 1;
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}
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