luke
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  • Joined on 2024-06-02
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verilator
SystemVerilog 0 0
Verilator open-source SystemVerilog simulator and lint system
rtl verilog cpp compilers verilog-simulator verilator systemc system-verilog
Updated 2026-03-30 20:06:41 +02:00
yosys
C++ 0 0
Yosys Open SYnthesis Suite
Updated 2026-03-30 18:37:29 +02:00
ngspice
C 0 0
Updated 2026-03-30 16:08:41 +02:00
xschem
C 0 0
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2026-03-30 10:00:14 +02:00
sbt
Scala 0 0
sbt, the interactive build tool
scala zinc sbt build-tool
Updated 2026-03-30 05:13:06 +02:00
manta
Python 0 0
A configurable and approachable tool for FPGA debugging and rapid prototyping.
fpga verilog icestorm icestick debug xilinx
Updated 2026-03-29 05:44:03 +02:00
nextpnr
C++ 0 0
nextpnr portable FPGA place and route tool
Updated 2026-03-28 09:38:48 +01:00
iverilog
C++ 0 0
Icarus Verilog
Updated 2026-03-28 03:17:10 +01:00
OpenSTA
C++ 0 0
OpenSTA engine
Updated 2026-03-28 00:06:30 +01:00
sv2v
Haskell 0 0
SystemVerilog to Verilog conversion
verilog yosys systemverilog conversion
Updated 2026-03-27 23:46:29 +01:00
magic
C 0 0
Magic VLSI Layout Tool
Updated 2026-03-27 00:44:00 +01:00
openFPGALoader
C++ 0 0
Universal utility for programming FPGA
fpga xilinx bitstream trenz-gowin-littlebee arty lattice intel gowin cyclone
Updated 2026-03-25 16:57:09 +01:00
prjxray
Python 0 0
Documenting the Xilinx 7-series bit-stream format.
Updated 2026-03-24 17:02:55 +01:00
klayout
C++ 0 0
KLayout Main Sources
qt klayout gds2 eda
Updated 2026-03-23 21:42:49 +01:00
prjpeppercorn
Python 0 0
Project Peppercorn - GateMate FPGA Bitstream Documentation
Updated 2026-03-18 13:13:58 +01:00