luke
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  • Joined on 2024-06-02
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prjxray-db
Makefile 0 0
Project X-Ray Database: XC7 Series
Updated 2026-02-10 12:15:48 +01:00
nextpnr
C++ 0 0
nextpnr portable FPGA place and route tool
Updated 2026-02-10 11:55:42 +01:00
IHP-AnalogAcademy
Jupyter Notebook 0 0
Updated 2026-02-10 11:47:10 +01:00
verilator
SystemVerilog 0 0
Verilator open-source SystemVerilog simulator and lint system
rtl verilog cpp compilers verilog-simulator verilator systemc system-verilog
Updated 2026-02-10 08:46:04 +01:00
sbt
Scala 0 0
sbt, the interactive build tool
scala zinc sbt build-tool
Updated 2026-02-10 06:13:46 +01:00
yosys
C++ 0 0
Yosys Open SYnthesis Suite
Updated 2026-02-10 03:34:47 +01:00
ngspice
C 0 0
Updated 2026-02-09 17:01:19 +01:00
xschem
C 0 0
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2026-02-09 16:51:17 +01:00
prjpeppercorn
Python 0 0
Project Peppercorn - GateMate FPGA Bitstream Documentation
Updated 2026-02-09 14:09:15 +01:00
iverilog
C++ 0 0
Icarus Verilog
Updated 2026-02-09 08:08:30 +01:00
klayout
C++ 0 0
KLayout Main Sources
qt klayout gds2 eda
Updated 2026-02-08 20:33:12 +01:00
magic
C 0 0
Magic VLSI Layout Tool
Updated 2026-02-06 16:50:29 +01:00
OpenSTA
C++ 0 0
OpenSTA engine
Updated 2026-02-05 05:12:23 +01:00
openFPGALoader
C++ 0 0
Universal utility for programming FPGA
fpga xilinx bitstream trenz-gowin-littlebee arty lattice intel gowin cyclone
Updated 2026-02-03 17:42:24 +01:00
netgen
C 0 0
Netgen complete LVS tool for comparing SPICE or verilog netlists
Updated 2026-02-03 08:00:02 +01:00