added test

ivtest/ivltests/sv_argumentless_func.v

@@ -0,0 +1,29 @@
+
+module test;
+
+function automatic [7:0] test_func;
+    input _unused;
+    test_func = _unused;
+endfunction
+
+logic [7:0] test_assign;
+assign test_assign = test_func(0);
+
+wire [7:0] test_wire = test_func(0);
+
+initial begin
+    if (test_assign !== test_func(0)) begin
+        $display("FAILED -- test_assign=%h, expect %h", test_assign, test_func(0));
+        $finish;
+    end
+
+    if (test_wire !== test_func(0)) begin
+        $display("FAILED -- test_wire=%h, expect %h", test_wire, test_func(0));
+        $finish;
+    end
+
+    $display("PASSED");
+    $finish;
+end
+
+endmodule

ivtest/regress-vvp.list

@@ -56,6 +56,7 @@ sv_ap_uarray5			vvp_tests/sv_ap_uarray5.json
 sv_ap_uarray6			vvp_tests/sv_ap_uarray6.json
 sv_ap_uarray_fail1		vvp_tests/sv_ap_uarray_fail1.json
 sv_ap_uarray_fail2		vvp_tests/sv_ap_uarray_fail2.json
+sv_argumentless_func		vvp_tests/sv_argumentless_func.json
 sv_array_assign_fail1	vvp_tests/sv_array_assign_fail1.json
 sv_array_assign_fail2	vvp_tests/sv_array_assign_fail2.json
 sv_array_cassign6		vvp_tests/sv_array_cassign6.json

ivtest/vvp_tests/sv_argumentless_func.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_argumentless_func.v",
+    "iverilog-args" : [ "-g2012" ]
+}