Add regression test for synthesisable for loop check (issue #687)

ivtest/gold/br_gh687-vvp-stdout.gold

@@ -0,0 +1,10 @@
+0
+0
+0
+0
+0
+0
+0
+0
+0
+1

ivtest/ivltests/br_gh687.v

@@ -0,0 +1,25 @@
+module top;
+    logic [9:0] pipe = 0;
+    logic [4:0] i;
+    logic clk = 0;
+
+    always #1 clk = ~clk;
+
+    always_ff @(posedge clk) begin
+        for (i=0; i<9; i++) begin
+            pipe[i+1] <= pipe[i];
+        end
+        pipe[0] <= pipe[9];
+    end
+
+    initial begin
+        pipe[0] = 1'b1;
+        
+        for (int j=0; j<10; j++) begin
+            $display(pipe[9]);
+            #2;
+        end
+        
+        $finish(0);
+    end
+endmodule

ivtest/regress-vvp.list

@@ -23,6 +23,7 @@ br_gh383b			vvp_tests/br_gh383b.json
 br_gh383c			vvp_tests/br_gh383c.json
 br_gh383d			vvp_tests/br_gh383d.json
 br_gh440			vvp_tests/br_gh440.json
+br_gh687			vvp_tests/br_gh687.json
 br_gh939			vvp_tests/br_gh939.json
 br_gh1018			vvp_tests/br_gh1018.json
 br_gh1029			vvp_tests/br_gh1029.json

ivtest/vvp_tests/br_gh687.json

@@ -0,0 +1,6 @@
+{
+    "type"   : "normal",
+    "source" : "br_gh687.v",
+    "gold"   : "br_gh687",
+    "iverilog-args" : [ "-g2009" ]
+}