luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

For a part select driving another part select the extra bits must be 'bz. 

When a part select is driving another part select any bits outside the
original select must be 'bz instead of 'bx. If we initialize the temporary
buffer to 'bz this should work as required. It there are multiple drivers
then a resolver comes into play and this should not matter.
This commit is contained in:
Cary R 2009-08-25 16:53:29 -07:00 committed by Stephen Williams
parent a49463e728
commit e31b6bd20c
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
vvp/part.cc
View File

@ -86,7 +86,7 @@ void vvp_fun_part_sa::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
{
assert(bit.size() == wid);
vvp_vector4_t tmp (vwid, BIT4_X);
vvp_vector4_t tmp (vwid, BIT4_Z);
tmp.set_vec(base_, val_);
tmp.set_vec(base, bit);
recv_vec4(port, tmp, 0);
@ -176,7 +176,7 @@ void vvp_fun_part_aa::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
vvp_vector4_t*val = static_cast<vvp_vector4_t*>
(vvp_get_context_item(context, context_idx_));
vvp_vector4_t tmp (vwid, BIT4_X);
vvp_vector4_t tmp (vwid, BIT4_Z);
tmp.set_vec(base_, *val);
tmp.set_vec(base, bit);
recv_vec4(port, tmp, context);