Add regression test for module array port initializers

Check that initializers are supported for module array ports.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/module_port_array_init1.v

@@ -0,0 +1,23 @@
+// Check that initializers values are supported for module array ports
+
+module M (
+  input [31:0] x[0:1] = '{1, 2},
+  output reg [31:0] y[0:1] = '{3, 4}
+);
+
+  initial begin
+    #1
+    if (x[0] === 1 && x[1] === 2 && y[0] === 3 && y[1] === 4) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED");
+    end
+  end
+
+endmodule
+
+module test;
+
+  M i_m ();
+
+endmodule

ivtest/regress-vvp.list

@@ -35,6 +35,7 @@ memsynth1			vvp_tests/memsynth1.json
 module_ordered_list1		vvp_tests/module_ordered_list1.json
 module_ordered_list2		vvp_tests/module_ordered_list2.json
 module_port_array1		vvp_tests/module_port_array1.json
+module_port_array_init1		vvp_tests/module_port_array_init1.json
 param-width			vvp_tests/param-width.json
 param-width-vlog95		vvp_tests/param-width-vlog95.json
 pr1388974			vvp_tests/pr1388974.json

ivtest/vvp_tests/module_port_array_init1.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "module_port_array_init1.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}