Rewrite function parameter finding code
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500442e5c5
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@ -393,38 +393,35 @@ int draw_function(ivl_scope_t scope, ivl_scope_t parent)
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const char *funcname = ivl_scope_tname(scope);
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// This logic relies on the return value being the first port
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vhdl_function *func = NULL;
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int nports = ivl_scope_ports(scope);
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for (int i = 0; i < nports; i++) {
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ivl_signal_t sig = ivl_scope_port(scope, i);
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std::string signame = make_safe_name(sig);
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// The return type is worked out from the output port
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vhdl_function *func = new vhdl_function(funcname, NULL);
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int nsigs = ivl_scope_sigs(scope);
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for (int i = 0; i < nsigs; i++) {
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ivl_signal_t sig = ivl_scope_sig(scope, i);
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vhdl_type *sigtype = get_signal_type(sig);
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std::string signame = make_safe_name(sig);
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switch (ivl_signal_port(sig)) {
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case IVL_SIP_OUTPUT:
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{
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assert(func == NULL);
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func = new vhdl_function(funcname, sigtype);
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// The magic variable Verilog_Result holds the return value
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signame = "Verilog_Result";
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func->get_scope()->add_decl
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(new vhdl_var_decl(signame.c_str(), new vhdl_type(*sigtype)));
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}
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// The magic variable Verilog_Result holds the return value
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signame = "Verilog_Result";
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func->set_type(sigtype);
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func->get_scope()->add_decl
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(new vhdl_var_decl(signame.c_str(), new vhdl_type(*sigtype)));
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break;
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case IVL_SIP_INPUT:
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assert(func);
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func->add_param(new vhdl_param_decl(signame.c_str(), sigtype));
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break;
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default:
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assert(false);
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}
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remember_signal(sig, func->get_scope());
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rename_signal(sig, signame);
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}
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// Non-blocking assignment not allowed in functions
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func->get_scope()->set_allow_signal_assignment(false);
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@ -415,6 +415,7 @@ public:
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const std::string &get_name() const { return name_; }
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const vhdl_type *get_type() const;
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void set_type(vhdl_type *t) { type_ = t; }
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void set_initial(vhdl_expr *initial);
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bool has_initial() const { return initial_ != NULL; }
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protected:
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