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Generate process bodies in the right place

This commit is contained in:
Nick Gasson 2008-06-12 10:47:52 +01:00
parent 7eb41304e6
commit 46991aa65c
3 changed files with 18 additions and 6 deletions
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8
tgt-vhdl/expr.cc
View File

@ -55,6 +55,12 @@ static vhdl_expr *translate_number(ivl_expr_t e)
return new vhdl_const_bits(ivl_expr_bits(e));
}
static vhdl_expr *translate_unary(ivl_expr_t e)
{
std::cout << "Unary opcode " << ivl_expr_opcode(e) << std::endl;
return NULL;
}
/*
* Generate a VHDL expression from a Verilog expression.
*/
@ -69,6 +75,8 @@ vhdl_expr *translate_expr(ivl_expr_t e)
return translate_signal(e);
case IVL_EX_NUMBER:
return translate_number(e);
case IVL_EX_UNARY:
return translate_unary(e);
default:
error("No VHDL translation for expression at %s:%d (type = %d)",
ivl_expr_file(e), ivl_expr_lineno(e), type);

14
tgt-vhdl/stmt.cc
View File

@ -242,6 +242,8 @@ static int draw_delay(vhdl_process *proc, stmt_container *container,
static int draw_wait(vhdl_process *proc, stmt_container *container,
ivl_statement_t stmt)
{
ivl_statement_t sub_stmt = ivl_stmt_sub_stmt(stmt);
int nevents = ivl_stmt_nevent(stmt);
for (int i = 0; i < nevents; i++) {
ivl_event_t event = ivl_stmt_events(stmt, i);
@ -268,6 +270,7 @@ static int draw_wait(vhdl_process *proc, stmt_container *container,
if (proc->get_parent()->have_declared(signame)) {
proc->add_sensitivity(signame);
non_edges.push_back(signame);
break;
}
}
else {
@ -298,6 +301,7 @@ static int draw_wait(vhdl_process *proc, stmt_container *container,
(new vhdl_var_ref(ivl_signal_basename(sig),
vhdl_type::std_logic()));
test->add_expr(detect);
break;
}
}
}
@ -318,6 +322,7 @@ static int draw_wait(vhdl_process *proc, stmt_container *container,
(new vhdl_var_ref(ivl_signal_basename(sig),
vhdl_type::std_logic()));
test->add_expr(detect);
break;
}
}
}
@ -329,17 +334,18 @@ static int draw_wait(vhdl_process *proc, stmt_container *container,
(new vhdl_var_ref((*it + "'Event").c_str(),
vhdl_type::boolean()));
}
vhdl_if_stmt *edge_det = new vhdl_if_stmt(test);
container->add_stmt(edge_det);
container->add_stmt(new vhdl_if_stmt(test));
draw_stmt(proc, edge_det->get_then_container(), sub_stmt);
}
else {
// Don't bother generating an edge detector if there
// are no edge-triggered events
draw_stmt(proc, container, sub_stmt);
}
}
ivl_statement_t sub_stmt = ivl_stmt_sub_stmt(stmt);
draw_stmt(proc, container, sub_stmt);
return 0;
}

2
tgt-vhdl/vhdl_syntax.cc
View File

@ -567,10 +567,8 @@ void vhdl_if_stmt::emit(std::ofstream &of, int level) const
of << "if ";
test_->emit(of, level);
of << " then";
newline(of, level);
then_part_.emit(of, level);
of << "else";
newline(of, level);
else_part_.emit(of, level);
of << "end if;";
}