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Declare vhdl module ports inline, a la ansi-c 

Keep the entity/component/module port declarations in the module port
list of the generated code. This clarifies the generated code and
fixes a couple bugs for more complicated types.
This commit is contained in:
Stephen Williams 2011-06-02 19:11:20 -07:00
parent 22ab8e4a76
commit a4145534e4
3 changed files with 5 additions and 18 deletions
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18
vhdlpp/entity_emit.cc
View File

@ -62,19 +62,11 @@ int Entity::emit(ostream&out)
break;
case PORT_IN:
out << "input ";
if (decl.msb != decl.lsb)
out << "[" << decl.msb
<< ":" << decl.lsb << "] ";
out << port->name;
decl.emit(out, port->name);
break;
case PORT_OUT:
out << "output ";
if (decl.reg_flag)
out << "reg ";
if (decl.msb != decl.lsb)
out << "[" << decl.msb
<< ":" << decl.lsb << "] ";
out << port->name;
decl.emit(out, port->name);
break;
}
}
@ -83,12 +75,6 @@ int Entity::emit(ostream&out)
out << ";" << endl;
for (map<perm_string,VType::decl_t>::const_iterator cur = declarations_.begin()
; cur != declarations_.end() ; ++cur) {
cur->second.emit(out, cur->first);
}
errors += bind_arch_->emit(out, this);
out << "endmodule" << endl;

1
vhdlpp/vsignal.cc
View File

@ -39,5 +39,6 @@ int Signal::emit(ostream&out, Entity*, Architecture*)
VType::decl_t decl;
type_->elaborate(decl);
errors += decl.emit(out, name_);
out << ";" << endl;
return errors;
}

4
vhdlpp/vtype_emit.cc
View File

@ -39,7 +39,7 @@ int VType::decl_t::emit(ostream&out, perm_string name) const
out << "signed ";
if (msb != lsb)
out << "[" << msb << ":" << lsb << "] ";
out << name << ";" << endl;
out << name;
break;
case VType::VBOOL:
out << wire << " bool ";
@ -47,7 +47,7 @@ int VType::decl_t::emit(ostream&out, perm_string name) const
out << "signed ";
if (msb != lsb)
out << "[" << msb << ":" << lsb << "] ";
out << name << ";" << endl;
out << name;
break;
}