Initialization of bit/logic in module declaration

The module declaration should allow initialization of the bit and
logic data types.

For example:
$ cat clkgen.sv
module clkgen(output logic clk = 0, output bit p = 1);
initial begin
	#200;
	$display("p = %b", p);
	$finish;
end

initial forever #10 clk = ~clk;
endmodule

$ iverilog -g 2009 clkgen.sv

$ ./a.out
p = 1

Suggested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>

parse.y

@@ -2208,6 +2208,28 @@ port_declaration
 
 	pform_make_reginit(@7, name, $9);
 
+	delete[]$7;
+	$$ = ptmp;
+      }
+  | attribute_list_opt
+    K_output net_type_opt primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER '=' expression
+      { Module::port_t*ptmp;
+	perm_string name = lex_strings.make($7);
+	NetNet::Type t   = ($3 == NetNet::IMPLICIT) ? NetNet::IMPLICIT_REG : $3;
+
+	ptmp = pform_module_port_reference(name, @2.text,
+					   @2.first_line);
+	pform_module_define_port(@2, name, NetNet::POUTPUT,
+				 t, $4, $5, $6, $1);
+	port_declaration_context.port_type = NetNet::POUTPUT;
+	port_declaration_context.port_net_type = t;
+	port_declaration_context.var_type = $4;
+	port_declaration_context.sign_flag = $5;
+	delete port_declaration_context.range;
+	port_declaration_context.range = $6;
+
+	pform_make_reginit(@7, name, $9);
+
 	delete[]$7;
 	$$ = ptmp;
       }