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Add cmos/rcmos primitives. 

This patch adds the cmos and rcmos primitives.
This commit is contained in:
Cary R 2007-09-06 18:46:22 -07:00 committed by Stephen Williams
parent 203cb0f730
commit 7c852aa075
10 changed files with 190 additions and 656 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

391
design_dump.cc
View File

@ -373,6 +373,9 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
case BUFIF1:
o << "bufif1";
break;
case CMOS:
o << "cmos";
break;
case NAND:
o << "nand";
break;
@ -400,6 +403,9 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
case PULLUP:
o << "pullup";
break;
case RCMOS:
o << "rcmos";
break;
case RNMOS:
o << "rnmos";
break;
@ -1223,388 +1229,3 @@ void Design::dump(ostream&o) const
}
/*
* $Log: design_dump.cc,v $
* Revision 1.176 2007/06/02 03:42:12 steve
* Properly evaluate scope path expressions.
*
* Revision 1.175 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.174 2007/03/02 06:13:22 steve
* Add support for edge sensitive spec paths.
*
* Revision 1.173 2007/02/01 03:14:33 steve
* Detect and report arrays without index in net contexts.
*
* Revision 1.172 2007/01/16 05:44:14 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.171 2006/10/30 05:44:49 steve
* Expression widths with unsized literals are pseudo-infinite width.
*
* Revision 1.170 2006/10/03 05:06:00 steve
* Support real valued specify delays, properly scaled.
*
* Revision 1.169 2006/09/26 19:48:40 steve
* Missing PSpec.cc file.
*
* Revision 1.168 2006/09/23 04:57:19 steve
* Basic support for specify timing.
*
* Revision 1.167 2006/07/31 03:50:17 steve
* Add support for power in constant expressions.
*
* Revision 1.166 2006/06/18 04:15:50 steve
* Add support for system functions in continuous assignments.
*
* Revision 1.165 2006/04/10 00:37:42 steve
* Add support for generate loops w/ wires and gates.
*
* Revision 1.164 2006/02/02 02:43:57 steve
* Allow part selects of memory words in l-values.
*
* Revision 1.163 2005/08/27 04:32:08 steve
* Handle synthesis of fully packed case statements.
*
* Revision 1.162 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.161 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.160 2005/05/24 01:44:27 steve
* Do sign extension of structuran nets.
*
* Revision 1.159 2005/05/17 20:56:55 steve
* Parameters cannot have their width changed.
*
* Revision 1.158 2005/05/07 03:13:30 steve
* Include delay expressions for assignments in dump.
*
* Revision 1.157 2005/03/09 05:52:03 steve
* Handle case inequality in netlists.
*
* Revision 1.156 2005/02/08 00:12:36 steve
* Add the NetRepeat node, and code generator support.
*
* Revision 1.155 2005/02/03 04:56:20 steve
* laborate reduction gates into LPM_RED_ nodes.
*
* Revision 1.154 2005/01/24 05:28:30 steve
* Remove the NetEBitSel and combine all bit/part select
* behavior into the NetESelect node and IVL_EX_SELECT
* ivl_target expression type.
*
* Revision 1.153 2005/01/22 18:16:00 steve
* Remove obsolete NetSubnet class.
*
* Revision 1.152 2005/01/09 20:16:00 steve
* Use PartSelect/PV and VP to handle part selects through ports.
*
* Revision 1.151 2004/12/29 23:55:43 steve
* Unify elaboration of l-values for all proceedural assignments,
* including assing, cassign and force.
*
* Generate NetConcat devices for gate outputs that feed into a
* vector results. Use this to hande gate arrays. Also let gate
* arrays handle vectors of gates when the outputs allow for it.
*
* Revision 1.150 2004/12/11 02:31:25 steve
* Rework of internals to carry vectors through nexus instead
* of single bits. Make the ivl, tgt-vvp and vvp initial changes
* down this path.
*
* Revision 1.149 2004/10/04 01:10:52 steve
* Clean up spurious trailing white space.
*
* Revision 1.148 2004/05/31 23:34:36 steve
* Rewire/generalize parsing an elaboration of
* function return values to allow for better
* speed and more type support.
*
* Revision 1.147 2004/02/20 06:22:56 steve
* parameter keys are per_strings.
*
* Revision 1.146 2004/02/18 17:11:54 steve
* Use perm_strings for named langiage items.
*
* Revision 1.145 2003/12/17 16:52:39 steve
* Debug dumps for synth2.
*
* Revision 1.144 2003/07/26 03:34:42 steve
* Start handling pad of expressions in code generators.
*
* Revision 1.143 2003/07/05 20:42:08 steve
* Fix some enumeration warnings.
*
* Revision 1.142 2003/06/20 00:53:19 steve
* Module attributes from the parser
* through to elaborated form.
*
* Revision 1.141 2003/06/18 03:55:18 steve
* Add arithmetic shift operators.
*
* Revision 1.140 2003/05/30 02:55:32 steve
* Support parameters in real expressions and
* as real expressions, and fix multiply and
* divide with real results.
*
* Revision 1.139 2003/04/22 04:48:29 steve
* Support event names as expressions elements.
*
* Revision 1.138 2003/03/10 23:40:53 steve
* Keep parameter constants for the ivl_target API.
*
* Revision 1.137 2003/01/27 05:09:17 steve
* Spelling fixes.
*
* Revision 1.136 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
*
* Revision 1.135 2002/10/23 01:47:17 steve
* Fix synth2 handling of aset/aclr signals where
* flip-flops are split by begin-end blocks.
*
* Revision 1.134 2002/10/19 22:59:49 steve
* Redo the parameter vector support to allow
* parameter names in range expressions.
*
* Revision 1.133 2002/08/19 00:06:11 steve
* Allow release to handle removal of target net.
*
* Revision 1.132 2002/08/13 05:35:00 steve
* Do not elide named blocks.
*
* Revision 1.131 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.130 2002/08/04 18:28:14 steve
* Do not use hierarchical names of memories to
* generate vvp labels. -tdll target does not
* used hierarchical name string to look up the
* memory objects in the design.
*
* Revision 1.129 2002/06/19 04:20:03 steve
* Remove NetTmp and add NetSubnet class.
*
* Revision 1.128 2002/06/14 21:38:41 steve
* Fix expression width for repeat concatenations.
*
* Revision 1.127 2002/06/08 23:42:46 steve
* Add NetRamDq synthsesis from memory l-values.
*
* Revision 1.126 2002/06/05 03:44:25 steve
* Add support for memory words in l-value of
* non-blocking assignments, and remove the special
* NetAssignMem_ and NetAssignMemNB classes.
*
* Revision 1.125 2002/06/04 05:38:44 steve
* Add support for memory words in l-value of
* blocking assignments, and remove the special
* NetAssignMem class.
*
* Revision 1.124 2002/05/26 01:39:02 steve
* Carry Verilog 2001 attributes with processes,
* all the way through to the ivl_target API.
*
* Divide signal reference counts between rval
* and lval references.
*
* Revision 1.123 2002/05/05 21:11:49 steve
* Put off evaluation of concatenation repeat expresions
* until after parameters are defined. This allows parms
* to be used in repeat expresions.
*
* Add the builtin $signed system function.
*
* Revision 1.122 2002/03/09 02:10:22 steve
* Add the NetUserFunc netlist node.
*
* Revision 1.121 2001/12/31 00:03:05 steve
* Include s indicator in dump of signed numbers.
*
* Revision 1.120 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.119 2001/11/19 01:46:38 steve
* Print typename is fallback expression node dump.
*
* Revision 1.118 2001/10/19 21:53:24 steve
* Support multiple root modules (Philip Blundell)
*
* Revision 1.117 2001/08/25 23:50:02 steve
* Change the NetAssign_ class to refer to the signal
* instead of link into the netlist. This is faster
* and uses less space. Make the NetAssignNB carry
* the delays instead of the NetAssign_ lval objects.
*
* Change the vvp code generator to support multiple
* l-values, i.e. concatenations of part selects.
*
* Revision 1.116 2001/07/27 04:51:44 steve
* Handle part select expressions as variants of
* NetESignal/IVL_EX_SIGNAL objects, instead of
* creating new and useless temporary signals.
*
* Revision 1.115 2001/07/27 02:41:55 steve
* Fix binding of dangling function ports. do not elide them.
*
* Revision 1.114 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.113 2001/04/29 20:19:10 steve
* Add pullup and pulldown devices.
*
* Revision 1.112 2001/04/22 23:09:46 steve
* More UDP consolidation from Stephan Boettcher.
*
* Revision 1.111 2001/02/17 05:13:36 steve
* Check that the port really exists here.
*
* Revision 1.110 2001/01/18 03:16:35 steve
* NetMux needs a scope. (PR#115)
*
* Revision 1.109 2001/01/13 22:20:08 steve
* Parse parameters within nested scopes.
*
* Revision 1.108 2000/12/16 01:45:47 steve
* Detect recursive instantiations (PR#2)
*
* Revision 1.107 2000/12/11 00:31:43 steve
* Add support for signed reg variables,
* simulate in t-vvm signed comparisons.
*
* Revision 1.106 2000/12/10 06:41:59 steve
* Support delays on continuous assignment from idents. (PR#40)
*
* Revision 1.105 2000/12/04 17:37:03 steve
* Add Attrib class for holding NetObj attributes.
*
* Revision 1.104 2000/11/11 01:52:09 steve
* change set for support of nmos, pmos, rnmos, rpmos, notif0, and notif1
* change set to correct behavior of bufif0 and bufif1
* (Tim Leight)
*
* Also includes fix for PR#27
*
* Revision 1.103 2000/11/11 00:03:36 steve
* Add support for the t-dll backend grabing flip-flops.
*
* Revision 1.102 2000/11/04 06:36:24 steve
* Apply sequential UDP rework from Stephan Boettcher (PR#39)
*
* Revision 1.101 2000/10/28 00:51:41 steve
* Add scope to threads in vvm, pass that scope
* to vpi sysTaskFunc objects, and add vpi calls
* to access that information.
*
* $display displays scope in %m (PR#1)
*
* Revision 1.100 2000/10/07 19:45:42 steve
* Put logic devices into scopes.
*
* Revision 1.99 2000/10/06 23:46:50 steve
* ivl_target updates, including more complete
* handling of ivl_nexus_t objects. Much reduced
* dependencies on pointers to netlist objects.
*
* Revision 1.98 2000/09/26 01:35:42 steve
* Remove the obsolete NetEIdent class.
*
* Revision 1.97 2000/09/17 21:26:15 steve
* Add support for modulus (Eric Aardoom)
*
* Revision 1.96 2000/09/10 02:18:16 steve
* elaborate complex l-values
*
* Revision 1.95 2000/09/02 20:54:20 steve
* Rearrange NetAssign to make NetAssign_ separate.
*
* Revision 1.94 2000/07/30 18:25:43 steve
* Rearrange task and function elaboration so that the
* NetTaskDef and NetFuncDef functions are created during
* signal enaboration, and carry these objects in the
* NetScope class instead of the extra, useless map in
* the Design class.
*
* Revision 1.93 2000/07/29 03:55:38 steve
* fix problem coalescing events w/ probes.
*
* Revision 1.92 2000/07/27 05:13:44 steve
* Support elaboration of disable statements.
*
* Revision 1.91 2000/07/22 22:09:03 steve
* Parse and elaborate timescale to scopes.
*
* Revision 1.90 2000/07/14 06:12:57 steve
* Move inital value handling from NetNet to Nexus
* objects. This allows better propogation of inital
* values.
*
* Clean up constant propagation a bit to account
* for regs that are not really values.
*
* Revision 1.89 2000/07/07 04:53:53 steve
* Add support for non-constant delays in delay statements,
* Support evaluating ! in constant expressions, and
* move some code from netlist.cc to net_proc.cc.
*
* Revision 1.88 2000/06/25 19:59:42 steve
* Redesign Links to include the Nexus class that
* carries properties of the connected set of links.
*
* Revision 1.87 2000/06/24 22:55:19 steve
* Get rid of useless next_link method.
*
* Revision 1.86 2000/06/13 03:24:48 steve
* Index in memory assign should be a NetExpr.
*
* Revision 1.85 2000/05/11 23:37:27 steve
* Add support for procedural continuous assignment.
*
* Revision 1.84 2000/05/07 18:20:07 steve
* Import MCD support from Stephen Tell, and add
* system function parameter support to the IVL core.
*
* Revision 1.83 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.82 2000/05/04 03:37:58 steve
* Add infrastructure for system functions, move
* $time to that structure and add $random.
*
* Revision 1.81 2000/05/02 03:13:30 steve
* Move memories to the NetScope object.
*
* Revision 1.80 2000/05/02 00:58:11 steve
* Move signal tables to the NetScope class.
*
* Revision 1.79 2000/04/28 21:00:29 steve
* Over agressive signal elimination in constant probadation.
*
* Revision 1.78 2000/04/23 03:45:24 steve
* Add support for the procedural release statement.
*
* Revision 1.77 2000/04/22 04:20:19 steve
* Add support for force assignment.
*
* Revision 1.76 2000/04/12 20:02:52 steve
* Finally remove the NetNEvent and NetPEvent classes,
* Get synthesis working with the NetEvWait class,
* and get started supporting multiple events in a
* wait in vvm.
*/

8
elaborate.cc
View File

@ -457,6 +457,10 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::BUFIF1, instance_width);
break;
case CMOS:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::CMOS, instance_width);
break;
case NAND:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::NAND, instance_width);
@ -485,6 +489,10 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::OR, instance_width);
break;
case RCMOS:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::RCMOS, instance_width);
break;
case RNMOS:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::RNMOS, instance_width);

70
ivl_target.h
View File

@ -209,6 +209,7 @@ typedef enum ivl_logic_e {
IVL_LO_BUFIF0 = 3,
IVL_LO_BUFIF1 = 4,
IVL_LO_BUFZ = 5,
IVL_LO_CMOS = 22,
IVL_LO_NAND = 6,
IVL_LO_NMOS = 7,
IVL_LO_NOR = 8,
@ -218,6 +219,7 @@ typedef enum ivl_logic_e {
IVL_LO_OR = 12,
IVL_LO_PULLDOWN = 13,
IVL_LO_PULLUP = 14,
IVL_LO_RCMOS = 23,
IVL_LO_RNMOS = 15,
IVL_LO_RPMOS = 16,
IVL_LO_PMOS = 17,
@ -1782,72 +1784,4 @@ typedef int (*target_design_f)(ivl_design_t des);
_END_DECL
/*
* $Log: ivl_target.h,v $
* Revision 1.182 2007/04/02 01:12:34 steve
* Seperate arrayness from word count
*
* Revision 1.181 2007/03/22 16:08:16 steve
* Spelling fixes from Larry
*
* Revision 1.180 2007/03/02 06:13:22 steve
* Add support for edge sensitive spec paths.
*
* Revision 1.179 2007/03/01 06:19:38 steve
* Add support for conditional specify delay paths.
*
* Revision 1.178 2007/02/26 19:49:49 steve
* Spelling fixes (larry doolittle)
*
* Revision 1.177 2007/02/25 23:08:24 steve
* Process Verilog escape sequences much earlier.
*
* Revision 1.176 2007/02/02 04:33:00 steve
* Use inttypes.h instead of stdint.h for portability.
*
* Revision 1.175 2007/01/29 01:52:51 steve
* Clarify the use of ivl_scope_def for not-functions.
*
* Revision 1.174 2007/01/17 05:00:12 steve
* Dead code for memories in scopes.
*
* Revision 1.173 2007/01/17 04:39:18 steve
* Remove dead code related to memories.
*
* Revision 1.172 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.171 2006/09/23 04:57:19 steve
* Basic support for specify timing.
*
* Revision 1.170 2006/08/08 05:11:37 steve
* Handle 64bit delay constants.
*
* Revision 1.169 2006/07/30 02:51:35 steve
* Fix/implement signed right shift.
*
* Revision 1.168 2006/06/18 04:15:50 steve
* Add support for system functions in continuous assignments.
*
* Revision 1.167 2006/04/16 00:15:43 steve
* Fix part selects in l-values.
*
* Revision 1.166 2006/04/10 00:37:42 steve
* Add support for generate loops w/ wires and gates.
*
* Revision 1.165 2006/02/02 02:43:58 steve
* Allow part selects of memory words in l-values.
*
* Revision 1.164 2006/01/02 05:33:19 steve
* Node delays can be more general expressions in structural contexts.
*
* Revision 1.163 2005/12/22 15:44:29 steve
* Document binary expression use.
*
* Revision 1.162 2005/11/20 15:58:25 steve
* Document the IVL_ST_DELAY statements.
*/
#endif

4
netlist.h
View File

@ -1446,8 +1446,8 @@ class NetLiteral : public NetNode {
class NetLogic : public NetNode {
public:
enum TYPE { AND, BUF, BUFIF0, BUFIF1, NAND, NMOS, NOR, NOT,
NOTIF0, NOTIF1, OR, PULLDOWN, PULLUP, RNMOS, RPMOS,
enum TYPE { AND, BUF, BUFIF0, BUFIF1, CMOS, NAND, NMOS, NOR, NOT,
NOTIF0, NOTIF1, OR, PULLDOWN, PULLUP, RCMOS, RNMOS, RPMOS,
PMOS, XNOR, XOR };
explicit NetLogic(NetScope*s, perm_string n, unsigned pins,

7
pform_dump.cc
View File

@ -395,6 +395,12 @@ void PGBuiltin::dump(ostream&out, unsigned ind) const
case PGBuiltin::PMOS:
out << "pmos ";
break;
case PGBuiltin::RCMOS:
out << "rcmos ";
break;
case PGBuiltin::CMOS:
out << "cmos ";
break;
default:
out << "builtin gate ";
}
@ -1077,3 +1083,4 @@ void PUdp::dump(ostream&out) const
out << "endprimitive" << endl;
}

181
t-dll.cc
View File

@ -807,6 +807,9 @@ void dll_target::logic(const NetLogic*net)
case NetLogic::BUFIF1:
obj->type_ = IVL_LO_BUFIF1;
break;
case NetLogic::CMOS:
obj->type_ = IVL_LO_CMOS;
break;
case NetLogic::NAND:
obj->type_ = IVL_LO_NAND;
break;
@ -834,6 +837,9 @@ void dll_target::logic(const NetLogic*net)
case NetLogic::PULLUP:
obj->type_ = IVL_LO_PULLUP;
break;
case NetLogic::RCMOS:
obj->type_ = IVL_LO_RCMOS;
break;
case NetLogic::RNMOS:
obj->type_ = IVL_LO_RNMOS;
break;
@ -2252,178 +2258,3 @@ bool dll_target::signal_paths(const NetNet*net)
extern const struct target tgt_dll = { "dll", &dll_target_obj };
/*
* $Log: t-dll.cc,v $
* Revision 1.171 2007/06/02 03:42:13 steve
* Properly evaluate scope path expressions.
*
* Revision 1.170 2007/04/02 01:12:34 steve
* Seperate arrayness from word count
*
* Revision 1.169 2007/03/26 20:32:47 steve
* More efficient allocate of ivl_nexus_t objects.
*
* Revision 1.168 2007/03/26 18:17:51 steve
* Remove pretense of general use for t_cookie.
*
* Revision 1.167 2007/03/26 16:51:49 steve
* do not calculate nexus name unless needed.
*
* Revision 1.166 2007/03/02 06:13:22 steve
* Add support for edge sensitive spec paths.
*
* Revision 1.165 2007/03/01 06:19:39 steve
* Add support for conditional specify delay paths.
*
* Revision 1.164 2007/01/29 01:52:51 steve
* Clarify the use of ivl_scope_def for not-functions.
*
* Revision 1.163 2007/01/17 05:00:12 steve
* Dead code for memories in scopes.
*
* Revision 1.162 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.161 2006/11/10 05:44:45 steve
* Process delay paths in second path over signals.
*
* Revision 1.160 2006/10/15 03:25:58 steve
* More detailed internal error message.
*
* Revision 1.159 2006/09/28 00:29:49 steve
* Allow specparams as constants in expressions.
*
* Revision 1.158 2006/09/23 04:57:19 steve
* Basic support for specify timing.
*
* Revision 1.157 2006/06/18 04:15:50 steve
* Add support for system functions in continuous assignments.
*
* Revision 1.156 2006/04/10 00:37:42 steve
* Add support for generate loops w/ wires and gates.
*
* Revision 1.155 2006/01/02 05:33:19 steve
* Node delays can be more general expressions in structural contexts.
*
* Revision 1.154 2005/08/06 17:58:16 steve
* Implement bi-directional part selects.
*
* Revision 1.153 2005/07/11 16:56:51 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.152 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.151 2005/06/26 18:08:46 steve
* Fix uninitialzied attr pointers for UDP devices.
*
* Revision 1.150 2005/05/24 01:44:28 steve
* Do sign extension of structuran nets.
*
* Revision 1.149 2005/05/08 23:44:08 steve
* Add support for variable part select.
*
* Revision 1.148 2005/04/24 23:44:02 steve
* Update DFF support to new data flow.
*
* Revision 1.147 2005/04/06 05:29:08 steve
* Rework NetRamDq and IVL_LPM_RAM nodes.
*
* Revision 1.146 2005/04/01 06:04:30 steve
* Clean up handle of UDPs.
*
* Revision 1.145 2005/03/18 02:56:04 steve
* Add support for LPM_UFUNC user defined functions.
*
* Revision 1.144 2005/03/12 06:43:36 steve
* Update support for LPM_MOD.
*
* Revision 1.143 2005/03/09 05:52:04 steve
* Handle case inequality in netlists.
*
* Revision 1.142 2005/02/19 02:43:38 steve
* Support shifts and divide.
*
* Revision 1.141 2005/02/13 01:15:07 steve
* Replace supply nets with wires connected to pullup/down supply devices.
*
* Revision 1.140 2005/02/12 06:25:40 steve
* Restructure NetMux devices to pass vectors.
* Generate NetMux devices from ternary expressions,
* Reduce NetMux devices to bufif when appropriate.
*
* Revision 1.139 2005/02/08 00:12:36 steve
* Add the NetRepeat node, and code generator support.
*
* Revision 1.138 2005/02/03 04:56:20 steve
* laborate reduction gates into LPM_RED_ nodes.
*
* Revision 1.137 2005/01/28 05:39:33 steve
* Simplified NetMult and IVL_LPM_MULT.
*
* Revision 1.136 2005/01/22 01:06:55 steve
* Change case compare from logic to an LPM node.
*
* Revision 1.135 2005/01/16 04:20:32 steve
* Implement LPM_COMPARE nodes as two-input vector functors.
*
* Revision 1.134 2005/01/09 20:16:01 steve
* Use PartSelect/PV and VP to handle part selects through ports.
*
* Revision 1.133 2004/12/29 23:55:43 steve
* Unify elaboration of l-values for all proceedural assignments,
* including assing, cassign and force.
*
* Generate NetConcat devices for gate outputs that feed into a
* vector results. Use this to hande gate arrays. Also let gate
* arrays handle vectors of gates when the outputs allow for it.
*
* Revision 1.132 2004/12/11 02:31:28 steve
* Rework of internals to carry vectors through nexus instead
* of single bits. Make the ivl, tgt-vvp and vvp initial changes
* down this path.
*
* Revision 1.131 2004/10/04 01:10:55 steve
* Clean up spurious trailing white space.
*
* Revision 1.130 2004/06/30 02:16:27 steve
* Implement signed divide and signed right shift in nets.
*
* Revision 1.129 2004/02/20 18:53:35 steve
* Addtrbute keys are perm_strings.
*
* Revision 1.128 2004/02/20 06:22:58 steve
* parameter keys are per_strings.
*
* Revision 1.127 2004/02/19 06:57:10 steve
* Memory and Event names use perm_string.
*
* Revision 1.126 2004/02/18 17:11:58 steve
* Use perm_strings for named langiage items.
*
* Revision 1.125 2003/12/12 05:43:08 steve
* Some systems dlsym requires leading _ or not on whim.
*
* Revision 1.124 2003/11/26 01:37:38 steve
* Warning about sprintf.
*
* Revision 1.123 2003/11/13 05:55:33 steve
* Move the DLL= flag to target config files.
*
* Revision 1.122 2003/11/10 20:59:04 steve
* Design::get_flag returns const char* instead of string.
*
* Revision 1.121 2003/09/03 23:33:29 steve
* Pass FF synchronous set values to code generator.
*
* Revision 1.120 2003/08/22 04:14:33 steve
* Fix uninitialized sset member.
*
* Revision 1.119 2003/08/15 02:23:53 steve
* Add synthesis support for synchronous reset.
*/

12
tgt-vvp/vvp_scope.c
View File

@ -1349,6 +1349,10 @@ static void draw_logic_in_scope(ivl_net_logic_t lptr)
ltype = "XOR";
break;
case IVL_LO_CMOS:
ltype = "CMOS";
break;
case IVL_LO_PMOS:
ltype = "PMOS";
break;
@ -1357,6 +1361,10 @@ static void draw_logic_in_scope(ivl_net_logic_t lptr)
ltype = "NMOS";
break;
case IVL_LO_RCMOS:
ltype = "RCMOS";
break;
case IVL_LO_RPMOS:
ltype = "RPMOS";
break;
@ -2408,7 +2416,3 @@ int draw_scope(ivl_scope_t net, ivl_scope_t parent)
return 0;
}
/*
* $Log: vvp_scope.c,v $
*/

7
vvp/logic.cc
View File

@ -575,12 +575,18 @@ void compile_functor(char*label, char*type, unsigned width,
} else if (strcmp(type, "MUXZ") == 0) {
obj = new vvp_fun_muxz(width);
} else if (strcmp(type, "CMOS") == 0) {
obj = new vvp_fun_cmos();
} else if (strcmp(type, "NMOS") == 0) {
obj = new vvp_fun_pmos(true);
} else if (strcmp(type, "PMOS") == 0) {
obj = new vvp_fun_pmos(false);
} else if (strcmp(type, "RCMOS") == 0) {
obj = new vvp_fun_rcmos();
} else if (strcmp(type, "RNMOS") == 0) {
obj = new vvp_fun_rpmos(true);
@ -635,3 +641,4 @@ void compile_functor(char*label, char*type, unsigned width,
define_functor_symbol(label, net_drv);
free(label);
}

111
vvp/npmos.cc
View File

@ -119,19 +119,104 @@ void vvp_fun_rpmos::recv_vec8(vvp_net_ptr_t ptr, vvp_vector8_t bit)
generate_output_(ptr);
}
/*
* $Log: npmos.cc,v $
* Revision 1.14 2007/06/12 02:25:00 steve
* Do not propogate until initialized.
*
* Revision 1.13 2005/06/22 00:04:49 steve
* Reduce vvp_vector4 copies by using const references.
*
* Revision 1.12 2005/06/12 15:13:37 steve
* Support resistive mos devices.
*
* Revision 1.11 2005/06/12 00:44:49 steve
* Implement nmos and pmos devices.
*
* CMOS primitive.
*/
vvp_fun_cmos_::vvp_fun_cmos_()
{
}
void vvp_fun_cmos_::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t &bit)
{
/* Data input is processed through the recv_vec8 method,
because the strength must be preserved. */
if (ptr.port() == 0) {
vvp_vector8_t tmp = bit;
recv_vec8(ptr, tmp);
return;
}
if (ptr.port() != 1 && ptr.port() != 2)
return;
if (ptr.port() == 1)
n_en_ = bit;
else
p_en_ = bit;
generate_output_(ptr);
}
#include <iostream>
void vvp_fun_cmos_::generate_output_(vvp_net_ptr_t ptr)
{
vvp_vector8_t out (bit_.size());
for (unsigned idx = 0 ; idx < out.size() ; idx += 1) {
vvp_bit4_t b_n_en = n_en_.value(idx);
vvp_bit4_t b_p_en = p_en_.value(idx);
vvp_scalar_t b_bit = bit_.value(idx);
if (b_n_en == BIT4_1 || b_p_en == BIT4_0) {
out.set_bit(idx, b_bit);
} else if (b_n_en == BIT4_0 && b_p_en == BIT4_1) {
out.set_bit(idx, vvp_scalar_t(BIT4_Z,0,0));
} else {
switch (b_bit.value()) {
case BIT4_0:
b_bit = vvp_scalar_t(BIT4_X,b_bit.strength0(),0);
break;
case BIT4_1:
b_bit = vvp_scalar_t(BIT4_X,0,b_bit.strength1());
break;
default:
break;
}
out.set_bit(idx, b_bit);
}
}
if (out.size() > 0)
vvp_send_vec8(ptr.ptr()->out, out);
}
vvp_fun_cmos::vvp_fun_cmos()
: vvp_fun_cmos_()
{
}
void vvp_fun_cmos::recv_vec8(vvp_net_ptr_t ptr, vvp_vector8_t bit)
{
if (ptr.port() == 1 || ptr.port() == 2) {
recv_vec4(ptr, reduce4(bit));
return;
}
if (ptr.port() != 0)
return;
bit_ = bit;
generate_output_(ptr);
}
vvp_fun_rcmos::vvp_fun_rcmos()
: vvp_fun_cmos_()
{
}
void vvp_fun_rcmos::recv_vec8(vvp_net_ptr_t ptr, vvp_vector8_t bit)
{
if (ptr.port() == 1) {
recv_vec4(ptr, reduce4(bit));
return;
}
if (ptr.port() != 0)
return;
bit_ = resistive_reduction(bit);
generate_output_(ptr);
}

55
vvp/npmos.h
View File

@ -83,15 +83,52 @@ class vvp_fun_rpmos : public vvp_fun_pmos_ {
};
/*
* $Log: npmos.h,v $
* Revision 1.8 2005/06/22 00:04:49 steve
* Reduce vvp_vector4 copies by using const references.
*
* Revision 1.7 2005/06/12 15:13:37 steve
* Support resistive mos devices.
*
* Revision 1.6 2005/06/12 00:44:49 steve
* Implement nmos and pmos devices.
* The truth table for the CMOS device is:
*
* Q = D N P (D is port0, N is port1, P is port2)
* ---------
* 0 | 0 0 0
* Z | 0 0 1
* 0 | 0 1 0
* 0 | 0 1 1
* L | 0 0 x
* L | 0 x 1
* L | 0 x x
* 1 | 1 0 0
* Z | 1 0 1
* 1 | 1 1 0
* 1 | 1 1 1
* H | 1 0 x
* H | 1 x 1
* H | 1 x x
*/
class vvp_fun_cmos_ : public vvp_net_fun_t {
public:
explicit vvp_fun_cmos_();
void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t &bit);
protected:
void generate_output_(vvp_net_ptr_t port);
vvp_vector8_t bit_;
vvp_vector4_t n_en_;
vvp_vector4_t p_en_;
};
class vvp_fun_cmos : public vvp_fun_cmos_ {
public:
explicit vvp_fun_cmos();
void recv_vec8(vvp_net_ptr_t port, vvp_vector8_t bit);
};
class vvp_fun_rcmos : public vvp_fun_cmos_ {
public:
explicit vvp_fun_rcmos();
void recv_vec8(vvp_net_ptr_t port, vvp_vector8_t bit);
};
#endif